公开(公告)号：WO1999032955A2

公开(公告)日：1999-07-01

申请号：PCT/US1997023636

申请日：1997-12-19

Applicant: BULL HN INFORMATION SYSTEMS INC.

Inventor： BULL HN INFORMATION SYSTEMS INC. ,  SHELLY, William, A. ,  INOSHITA, Minoru ,  BARYLA, Robert, J.

IPC: G06F00/00

CPC classification number: G06F12/0859 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a "siphon" operation to service the request of the other CPU.

Abstract translation: 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和高速缓存控制器，其具有：用于识别驻留在高速缓冲存储器中的信息块的处理器目录，用于识别来自CPU的请求上的高速缓存未命中的逻辑，用于存储错过块的标识的高速缓存未命中输出缓冲器 以及要从高速缓冲存储器移出的块以便为所请求的块腾出空间，并且用于选择性地将标识发送到CPU总线上，用于存储所有最近错过的块的标识的高速缓存未命中输入缓冲堆栈和要从所有块中交换的块的标识 组中的CPU，用于将高速缓存未命中输出缓冲器堆栈中的标识与高速缓存未命中输入缓冲器堆栈和控制逻辑中的标识进行比较的比较器，响应于第一比较器感测到比较（指示另一CPU对于 块被交换），用于禁止将交换要求广播到CPU总线上，并将交换操作转换为“虹吸” 操作来服务其他CPU的请求。