公开(公告)号：WO2009006018A2

公开(公告)日：2009-01-08

申请号：PCT/US2008/067279

申请日：2008-06-18

Applicant: INTEL CORPORATION ,  PIAZZA, Thomas ,  DWYER, Michael ,  CHENG, Scott

Inventor： PIAZZA, Thomas ,  DWYER, Michael ,  CHENG, Scott

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0859

Abstract: According to one embodiment, the present disclosure generally provides a method for improving the performance of a cache of a processor. The method may include storing a plurality of data in a data Random Access Memory (RAM). The method may further include holding information for all outstanding requests forwarded to a next-level memory subsystem. The method may also include clearing information associated with a serviced request after the request has been fulfilled. The method may additionally include determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem. The method may further include matching fulfilled requests serviced by the next-level memory subsystem to at least one requestor who issued requests while an original request was in-flight to the next level memory subsystem. The method may also include storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color. The method may additionally include scheduling hit and miss data returns. Of course, various alternative embodiments are also within the scope of the present disclosure.

Abstract translation: 根据一个实施例，本公开通常提供用于提高处理器的高速缓存的性能的方法。 该方法可以包括将多个数据存储在数据随机存取存储器（RAM）中。 所述方法还可以包括保存转发到下一级存储器子系统的所有未完成请求的信息。 该方法还可以包括在请求已经满足之后清除与服务请求相关联的信息。 该方法可以另外包括确定后续请求是否匹配提供给已经在飞行中的一个或多个请求到下一级存储器子系统的地址。 该方法还可以包括将下一级存储器子系统服务的满足的请求与在原始请求正在进行到下一级存储器子系统时发出请求的至少一个请求者进行匹配。 所述方法还可以包括存储特定于每个请求的信息，所述信息包括集合属性和方式属性，所述设置和方式属性被配置为在数据返回后识别返回的数据应保存在数据RAM中的位置，所述信息 特定于每个请求还包括线程ID，指令队列位置和颜色中的至少一个。 该方法可以另外包括调度命中和未命中数据返回。 当然，各种替代实施例也在本公开的范围内。

公开(公告)号：WO2008090525A2

公开(公告)日：2008-07-31

申请号：PCT/IB2008/050262

申请日：2008-01-24

Applicant: NXP B.V. ,  VAN DE WAERDT, Jan-Willem

Inventor： VAN DE WAERDT, Jan-Willem

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0804 ,  G06F12/0859 ,  G06F2212/6028

Abstract: A computer system includes a data cache supported by a copy-back buffer and pre- allocation request stack. A programmable trigger mechanism inspects each store operation made by the processor to the data cache to see if a next cache line should be pre-allocated. If the store operation memory address occurs within a range defined by START and END programmable registers, then the next cache line that includes a memory address within that defined by a programmable STRIDE register is requested for pre-allocation. Bunches of pre-allocation requests are organized and scheduled by the pre-allocation request stack, and will take their turns to allow the cache lines being replaced to be processed through the copy-back buffer. By the time the processor gets to doing the store operation in the next cache line, such cache line has already been pre-allocated and there will be a cache hit, thus saving stall cycles.

Abstract translation: 计算机系统包括由回拷缓冲器和预分配请求堆栈支持的数据缓存。 可编程触发机制检查处理器对数据高速缓存所做的每个存储操作，以查看是否应预先分配下一个高速缓存行。 如果存储操作存储器地址出现在由START和END可编程寄存器定义的范围内，则包含由可编程STRIDE寄存器定义的存储器地址的下一个高速缓存行被请求用于预分配。 一系列预分配请求由预分配请求堆栈组织和调度，并且将轮流允许通过回拷缓冲区处理被替换的高速缓存行。 当处理器在下一个高速缓存行中执行存储操作时，这样的高速缓存行已经预先分配，并且会有高速缓存命中，从而节省了暂停周期。

公开(公告)号：WO2008047180A1

公开(公告)日：2008-04-24

申请号：PCT/IB2006/053875

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ZAMSKY, Ziv ,  ANSCHEL, Moshe ,  ELDAR, Alon ,  FLAT, Dmitry ,  GODIN, Kostantin ,  PELED, Itay ,  PELEG, Dvir

Inventor： ZAMSKY, Ziv ,  ANSCHEL, Moshe ,  ELDAR, Alon ,  FLAT, Dmitry ,  GODIN, Kostantin ,  PELED, Itay ,  PELEG, Dvir

IPC: G06F12/08

CPC classification number: G06F12/0859 ,  G06F9/3834 ,  G06F12/0862

Abstract: A device (10, 11) and a method (400, 500) for fetching an information unit, the method (400, 500) includes: receiving (410) a request to execute a write through cacheable operation of the information unit; emptying (440) a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining (450), when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing (460) the information unit to the cache module in response to the cache module in response to the determination.

Abstract translation: 一种用于获取信息单元的设备（10,11）和方法（400,500），所述方法（400,500）包括：接收（410）通过所述信息单元的可高速缓存操作执行写入的请求; 从数据中取出（440）取出单元，其中所述提取单元连接到高速缓存模块和高级存储单元; 确定（450）当所述提取单元为空时，所述高速缓存模块是否存储所述信息单元的旧版本; 以及响应于所述确定，响应于所述高速缓存模块，将所述信息单元选择性地写入（460）所述高速缓存模块。

公开(公告)号：WO2007137141A3

公开(公告)日：2008-02-28

申请号：PCT/US2007069188

申请日：2007-05-17

Applicant: QUALCOMM INC ,  AHMED MUHAMMAD

Inventor： AHMED MUHAMMAD

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/123 ,  G06F12/0859 ,  G06F12/126 ,  G06F12/128 ,  Y02D10/13

Abstract: Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag-miss allocation. Herein, steps forming a first-in, first-out (FIFO) replacement listing of victim ways for the cache memory, wherein the depth of the FIFO replacement listing approximately equals the number of ways in the cache set. The method and system place a victim way on the FIFO replacement listing only in the event that a tag-miss results in a tag-miss allocation, the victim way is placed at the tail of the FIFO replacement listing after any previously selected victim way. Use of a victim way on the FIFO replacement listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.

Abstract translation: 在基于CDMA的产品和服务中使用的技术，包括替换高速缓存存储器分配，以便在标签错失分配之后最大化多个设置路径的驻留。 这里，形成用于高速缓冲存储器的受害方式的先入先出（FIFO）替换列表的步骤，其中FIFO替换列表的深度近似等于高速缓存集中的路数。 只有在标签错失导致标签错失分配的情况下，该方法和系统才会将受害者的方式置于FIFO替换列表中，受害者的方式将放置在先前选择的受害方式之后的FIFO替换列表的尾部。 在受害者方式的不完整的先前分配的情况下，通过停止重用请求直到受害方的初始分配完成或重放重用请求直到这样的初始化 受害方的分配完成。

公开(公告)号：WO2006007264A3

公开(公告)日：2007-05-31

申请号：PCT/US2005019268

申请日：2005-06-01

Applicant: ATMEL CORP

Inventor： ADUSUMILLI VIJAYA P ,  TELECCO NICOLA ,  TEHRANI ABBAS S

IPC: G06F12/16 ,  G06F12/00 ,  G11C7/10 ,  G11C29/00

CPC classification number: G11C16/26 ,  G06F11/1068 ,  G06F12/0804 ,  G06F12/0859 ,  G06F2212/2022 ,  G11C16/102

Abstract: A system (300) and method for performing a simultaneous external read operation during internal programming of a memory device (301) is described. The memory device is configured to store data randomly and includes a source location (305), a destination location (303), a data register (307), and a cache register (309). The data register (307) is configured to simultaneously write data to the destination (303) and to the cache register (309). The system (300) further includes a processing device (107) (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device (107) is additionally configured to provide for error correction if the received data are inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location (303).

Abstract translation: 描述了一种用于在存储器件（301）的内部编程期间执行同时外部读取操作的系统（300）和方法。 存储器装置被配置为随机存储数据，并且包括源位置（305），目的地位置（303），数据寄存器（307）和高速缓存寄存器（309）。 数据寄存器（307）被配置为同时将数据写入目的地（303）和高速缓存寄存器（309）。 系统（300）还包括处理装置（107）（例如，微处理器或微控制器），用于验证通过与存储装置的电气通信接收的任何数据的准确性。 处理装置（107）另外配置成如果接收的数据不准确地提供错误校正，如果需要，则向随机数据添加随机数据，然后将经纠错和/或随机数据修改的数据传送回目的位置 （303）。

公开(公告)号：WO2006035370A3

公开(公告)日：2006-08-17

申请号：PCT/IB2005053109

申请日：2005-09-21

Applicant: FREESCALE SEMICONDUCTOR INC ,  GODIN KOSTANTIN ,  ANSCHEL MOSHE ,  EFRAT YACOV ,  ROZENSHEIN ZVIKA ,  ZAMSKY ZIV

Inventor： GODIN KOSTANTIN ,  ANSCHEL MOSHE ,  EFRAT YACOV ,  ROZENSHEIN ZVIKA ,  ZAMSKY ZIV

IPC: G06F12/00

CPC classification number: G06F12/0859 ,  G06F12/0862 ,  G06F12/0879 ,  G06F13/28

Abstract: Apparatus (100) and method (500) for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module (200), for initiating a. first and second requests to retrieve, from the cache module (200), a first and a second data unit; (ii) logic (210), adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller (212), connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the fin t and the second mandatory data units.

Abstract translation: 用于向高速缓存模块提供信息的设备（100）和方法（500）包括：（i）至少一个连接到高速缓存模块（200）的处理器，用于启动一个。 第一和第二请求从缓存模块（200）检索第一和第二数据单元; （ii）逻辑（210），适于接收所述请求并确定所述第一和第二数据单元是否是强制数据单元; 连接到高速缓存模块的控制器（212）适于在单次提取突发期间检索到的存储器空间包括第一和第二强制性数据单元时启动单个提取突发，并且适于发起多次获取突发，如果 在单个提取突发期间可检索的存储器空间不包括鳍片t和第二强制数据单元。

公开(公告)号：WO2006007264A2

公开(公告)日：2006-01-19

申请号：PCT/US2005/019268

申请日：2005-06-01

Applicant: ATMEL CORPORATION

Inventor： ADUSUMILLI, Vijaya, P. ,  TELECCO, Nicola ,  TEHRANI, Abbas, S.

IPC: G06F12/00

CPC classification number: G11C16/26 ,  G06F11/1068 ,  G06F12/0804 ,  G06F12/0859 ,  G06F2212/2022 ,  G11C16/102

Abstract: A system (300) and method for performing a simultaneous external read operation during internal programming of a memory device (301) is described. The memory device is configured to store data randomly and includes a source location (305), a destination location (303), a data register (307), and a cache register (309). The data register (307) is configured to simultaneously write data to the destination (303) and to the cache register (309). The system (300) further includes a processing device (107) (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device (107) is additionally configured to provide for error correction if the received data are inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location (303).

Abstract translation: 描述了一种用于在存储器件（301）的内部编程期间执行同时外部读取操作的系统（300）和方法。 存储器装置被配置为随机存储数据，并且包括源位置（305），目的地位置（303），数据寄存器（307）和高速缓存寄存器（309）。 数据寄存器（307）被配置为同时将数据写入目的地（303）和高速缓存寄存器（309）。 系统（300）还包括处理装置（107）（例如，微处理器或微控制器），用于验证通过与存储装置的电气通信接收的任何数据的准确性。 处理装置（107）另外配置成如果接收的数据不准确地提供错误校正，如果需要，则向随机数据添加随机数据，然后将经纠错和/或随机数据修改的数据传送回目的位置 （303）。

公开(公告)号：WO2003021409A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/027666

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： BIRK, Palle ,  SOERENSEN, Joern ,  ALLEN, Michael

IPC: G06F1/32

CPC classification number: G06F11/3636 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/4843 ,  G06F12/0842 ,  G06F12/0859 ,  G06F13/28 ,  G06F13/385 ,  G06F2213/3814 ,  H03L7/0802 ,  H03L7/095 ,  H03L7/183 ,  H04W88/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20 ,  Y02D70/1222 ,  Y02D70/124 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y10S331/02

Abstract: A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

Abstract translation: 提供动态功率控制器，其识别处理器的时钟频率要求并确定电压要求以支持时钟频率要求。 动态功率控制器将处理器转换到由时钟频率要求和电压要求所定义的功率状态。 具体地说，将由电压要求表示的电压电平提供给处理器，并将由频率要求表示的频率分布提供给处理器的时钟信号。

公开(公告)号：WO1999032955A2

公开(公告)日：1999-07-01

申请号：PCT/US1997023636

申请日：1997-12-19

Applicant: BULL HN INFORMATION SYSTEMS INC.

Inventor： BULL HN INFORMATION SYSTEMS INC. ,  SHELLY, William, A. ,  INOSHITA, Minoru ,  BARYLA, Robert, J.

IPC: G06F00/00

CPC classification number: G06F12/0859 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a "siphon" operation to service the request of the other CPU.

Abstract translation: 包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。 每个专用高速缓存包括高速缓冲存储器和高速缓存控制器，其具有：用于识别驻留在高速缓冲存储器中的信息块的处理器目录，用于识别来自CPU的请求上的高速缓存未命中的逻辑，用于存储错过块的标识的高速缓存未命中输出缓冲器 以及要从高速缓冲存储器移出的块以便为所请求的块腾出空间，并且用于选择性地将标识发送到CPU总线上，用于存储所有最近错过的块的标识的高速缓存未命中输入缓冲堆栈和要从所有块中交换的块的标识 组中的CPU，用于将高速缓存未命中输出缓冲器堆栈中的标识与高速缓存未命中输入缓冲器堆栈和控制逻辑中的标识进行比较的比较器，响应于第一比较器感测到比较（指示另一CPU对于 块被交换），用于禁止将交换要求广播到CPU总线上，并将交换操作转换为“虹吸” 操作来服务其他CPU的请求。

公开(公告)号：WO99027452A1

公开(公告)日：1999-06-03

申请号：PCT/US1998/025001

申请日：1998-11-19

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3802 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0859

Abstract: A memory cache sequencer circuit (10) manages the operation of a memory cache (12, 14, 16, 18) and cache buffer (30) so as to efficiently forward memory contents being delivered to the memory cache (12, 14, 16, 18) via the cache buffer (30), to a multithreading processor (6) awaiting return of those memory contents. The sequencer circuit (10) predicts the location of the memory contents that the processor (6) is awaiting, and speculatively forwards memory contents from either the cache buffer (30) or memory cache (12, 14, 16, 18), while simultaneously verifying that the speculatively forwarded memory contents were correctly forwarded. If the memory contents were incorrectly forwarded, the sequencer circuit (10) issues a signal to the processor (6) receiving the speculatively forwarded memory contents to ignore the forwarded memory contents. This speculative forwarding process may be performed, for example, when a memory access request is received from the processor (6), or whenever memory contents are delivered to the cache buffer (30) after a cache miss. The sequencer circuit (10) includes a plurality of sequencers (50), each storing information for managing the return of data in response to one of the potentially multiple misses and resulting cache linefills which can be generated by the multiple threads being executed by the processor (6).

Abstract translation: 存储器高速缓存定序器电路（10）管理存储器高速缓存（12,14,16,18）和高速缓冲存储器（30）的操作，以便有效地转发传送到存储器高速缓存（12,14,16,18） 18）通过高速缓冲存储器（30）传送到等待这些存储器内容返回的多线程处理器（6）。 定序器电路（10）预测处理器（6）正在等待的存储器内容的位置，并且从高速缓冲存储器（30）或存储器高速缓存（12,14,16,18）推测地转发存储器内容，同时 验证推测性转发的存储器内容是否正确转发。 如果存储器内容不正确地转发，则定序器电路（10）向接收推测性转发的存储器内容的处理器（6）发出信号，以忽略转发的存储器内容。 例如，当从处理器（6）接收到存储器访问请求时，或者当高速缓存未命中之后存储器内容被传送到高速缓冲存储器（30）时，可以执行该推测转发过程。 定序器电路（10）包括多个定序器（50），每个定序器（50）存储用于响应于潜在的多个未命中之一来管理数据的返回的信息，以及由处理器执行的多个线程可以产生的结果高速缓存行填充 （6）。