Abstract:
A structure and method for forming a column electrode for a field emission display device wherein the column electrode (702) is disposed beneath the field emitters and the row electrode. In one embodiment, the present invention comprises depositing a resistor layer (706) over portions of a column electrode (702). Next, an inter-metal dielectric layer (708) is deposited over the column electrode. In the present embodiment, the inter-metal dielectric layer (708) is deposited over portions of the resistor layer (706) and over pad areas (704a, 704b) of the column electrode (702). After the deposition of the inter-metal dielectric layer (708), the column electrode (702) is subjected to an anodization process such that the exposed regions of the column electrode (702) are anodized. In so doing, the present invention provides a column electrode structure (702) which is resistant to column to row electrode shorts and which is protected from subsequent processing steps.
Abstract:
A field emission display (700) having an improved operational life. In one embodiment, the field emission display (700) comprises a plurality of row lines (230), a plurality of column lines (250), and a plurality of electron emissive elements (40) disposed at intersections of the plurality of row lines (230) and column lines (250), a column driver circuit (740) and a row driver circuit (720). The column driver circuit (740) is coupled to drive column voltage signals over the plurality of column lines (250); and the row driver circuit (720) is coupled to activate and deactivate the plurality of row lines (230) with row voltage signals. According to the present invention, operation life of the field emission display is extended when the electron emissive elements are intermittently reverse-biased by the column voltage signals and the row voltage signals. In another embodiment, the row driver circuit is responsive to a SLEEP signal (770). The row driver circuit (720), upon receiving the SLEEP signal (770), drives a sleep-mode voltage over the row lines (230) to reverse-bias the electron emissive elements.
Abstract:
Method for compensating for brightness variations in a field emission device (100a). In one embodiment, a method and system are described for measuring the relative brightness of rows of a field emission display (FED) device (100a), storing information representing the measured brightness into a correction table and using the correction table to provide uniform row brightness in the display by adjusting row voltages and/or row on-time periods. A special measurement process is described for providing accurate current measurements on the rows. This embodiment compensates for brightness variations of the rows, e.g., for rows near the spacer walls (30). In another embodiment, a periodic signal, e.g., a high frequency noise signal (340), is added to the row on-time pulse in order to camouflage brightness variations in the rows near the spacer walls (30). In another embodiment, the area under the row on-time pulse is adjusted to provide row-by-row brightness compensation based on correction values stored in a memory resident correction table (60). In another embodiment, the brightness of each row is measured and compiled into a data profile for the FED. The data profile is used to control cathode burn-in processes so that brightness variations are corrected by physically altering the characteristics of the emitters of the rows.
Abstract:
A circuit and method for turning-on and turning-off elements of an field emission display device to protect against emitter electrode(60) and gate electrode(50) degradation. The circuit(910) includes control logic(916) having a sequencer which in one embodiment can be realized using a state machine. Upon power-on, the control logic sends an enable signal to a high voltage power supply (912) that supplies voltage to the anode electrode (914). At this time a low voltage power supply (918) and driving circuitry (920)are disabled. Upon receiving a confirmation signal from the high voltage power supply, the control logic enables the low voltage power supply which supplies voltage to the driving circuitry (920). Upon receiving a confirmation signal from the low voltage power supply (918), or optionally after expiration of a predetermined time period, the control logic (916) then enables the driving circuitry (920) which drives the gate electrodes (50) and the emitter electrodes (60) which make up the rows and columns of the FED device. Upon power down, the control logic (916) first disables the low voltage power supply (918), then the high voltage power supply (912).