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    RUN-TIME CODE PARALLELIZATION WITH INDEPENDENT SPECULATIVE COMMITTING OF INSTRUCTIONS PER SEGMENT
    1.
    发明申请
    RUN-TIME CODE PARALLELIZATION WITH INDEPENDENT SPECULATIVE COMMITTING OF INSTRUCTIONS PER SEGMENT 审中-公开
    运行时代码并行化，独立推测每段指令

    公开(公告)号：WO2017098344A1

    公开(公告)日：2017-06-15

    申请号：PCT/IB2016/055346

    申请日：2016-09-08

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： TENNENHAUS, Omri ,  MIZRAHI, Noam ,  MANDLER, Alberto

    IPC: G06F9/38

    CPC classification number: G06F9/3005 ,  G06F9/30098 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863

    Abstract: A method includes, in a processor (20) that processes multiple segments of a sequence of instructions of program code, wherein each segment is defined as either speculative or non- speculative, dispatching the instructions of the segments into at least one instruction buffer (44). The instructions of the segments are executed, and, in each segment, at least some of the executed instructions of the segment are speculatively-committed from the at least one instruction buffer independently of any other segment. Dispatching the instructions includes dispatching the instructions of a first segment into a first region of the at least one instruction buffer, and dispatching the instructions of a second segment, which occurs later in the program code than the first segment, into a second region of the at least one instruction buffer before all the instructions of the first segment have been dispatched into the first region.

    Abstract translation: 一种方法包括：在处理器（20）中处理程序代码的指令序列的多个段，其中每个段被定义为推测性或非推测性，调度段的指令 到至少一个指令缓冲器（44）中。 执行片段的指令，并且在每个片段中，独立于任何其它片段，从至少一个指令缓冲器推测性地提交片段的至少一些执行的指令。 分派指令包括将第一段的指令分派到至少一个指令缓冲器的第一区域中，并将稍后在程序代码中发生的第二段的指令分派到第一段的第二区域中 在第一段的所有指令已被分派到第一区域之前，至少有一个指令缓冲区。

    HARDWARE-BASED RUN-TIME MITIGATION OF CONDITIONAL BRANCHES
    2.
    发明申请
    HARDWARE-BASED RUN-TIME MITIGATION OF CONDITIONAL BRANCHES 审中-公开
    基于硬件的条件分支的运行时缓解

    公开(公告)号：WO2017072615A1

    公开(公告)日：2017-05-04

    申请号：PCT/IB2016/056042

    申请日：2016-10-09

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： FRIEDMANN, Jonathan ,  GOREN, Ido ,  KOREN, Shay ,  MIZRAHI, Noam ,  MANDLER, Alberto

    IPC: G06F9/44 ,  G06F9/38 ,  G06F9/318

    CPC classification number: G06F9/38 ,  G06F9/30

    Abstract: A method includes, in a processor (20), processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block (70) of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block (74) of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

    Abstract translation: 一种方法包括在处理器（20）中通过处理器的指令流水线来处理预编译指令序列。 指令的第一块（70）在经由流水线流动的指令中被识别。 第一块包括条件分支指令，该条件分支指令有条件地将指令的执行分成至少第一和第二流量控制轨迹，所述第一和第二流量控制轨迹在多个指令中彼此不同，并收敛于第一和第二流量控制轨迹再次共同的给定指令， 控制痕迹。 处理器在运行时创建指令的第二块（74），其在逻辑上等同于第一块但用单个流量控制轨迹代替第一和第二流量控制轨迹。 导致管道执行第二个块而不是第一个块。

    SINGLE-THREAD SPECULATIVE MULTI-THREADING
    3.
    发明申请
    SINGLE-THREAD SPECULATIVE MULTI-THREADING 审中-公开
    单线程的多线程

    公开(公告)号：WO2017199106A1

    公开(公告)日：2017-11-23

    申请号：PCT/IB2017/051585

    申请日：2017-03-19

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： FRIEDMANN, Jonathan ,  KOREN, Shay ,  MIZRAHI, Noam ,  MANDLER, Alberto

    IPC: G06F9/38

    CPC classification number: G06F9/3814 ,  G06F9/3005 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3861 ,  G06F9/3867

    Abstract: A processor (20) includes a pipeline (28, 32, 36, 44, 52) and control circuitry (60, 64, 68). The pipeline is configured to process instructions of program code and includes one or more fetch units (28). The control circuitry is configured to predict at run-time one or more future flow-control traces to be traversed in the program code, to define, based on the predicted flow-control traces, two or more regions of the program code from which instructions are to be fetched, wherein the number of regions is greater than the number of fetch units, and to instruct the pipeline to fetch instructions alternately from the two or more regions of the program code using the one or more fetch units, and to process the fetched instructions.

    Abstract translation: 处理器（20）包括流水线（28,32,36,44,52）和控制电路（60,64,68）。 流水线被配置为处理程序代码的指令并且包括一个或多个提取单元（28）。 控制电路被配置为在运行时预测要在程序代码中遍历的一个或多个将来的流量控制轨迹，基于预测的流量控制轨迹定义程序代码的两个或更多个区域， 将被提取，其中区域的数量大于提取单元的数量，并且指示流水线使用一个或多个提取单元从程序代码的两个或更多个区域中交替提取指令，并且处理 提取说明。

    RUN-TIME PARALLELIZATION OF CODE EXECUTION BASED ON AN APPROXIMATE REGISTER-ACCESS SPECIFICATION
    4.
    发明申请
    RUN-TIME PARALLELIZATION OF CODE EXECUTION BASED ON AN APPROXIMATE REGISTER-ACCESS SPECIFICATION 审中-公开
    基于近似寄存器访问规范的代码执行的运行时间并行

    公开(公告)号：WO2016170438A1

    公开(公告)日：2016-10-27

    申请号：PCT/IB2016/050562

    申请日：2016-02-04

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： MIZRAHI, Noam ,  MANDLER, Alberto ,  KOREN, Shay ,  FRIEDMANN, Jonathan

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/00

    CPC classification number: G06F9/3861 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/455 ,  G06F9/46 ,  G06F12/0833

    Abstract: A method includes, in a processor (20) that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.

    Abstract translation: 一种方法包括在处理程序代码指令的处理器（20）中处理指令的第一段。 使用指令的寄存器访问的近似规范，在第一段中标识一个或多个目的地寄存器。 目的地寄存器的相应值仅在验证该值对于根据近似规范由第二段读出有效时才可用于指令的第二段。 使用从第一段获得的值，至少部分地与第一段的处理并行处理第二段。

    RUN-TIME CODE PARALLELIZATION USING OUT-OF-ORDER RENAMING WITH PRE-ALLOCATION OF PHYSICAL REGISTERS
    5.
    发明申请
    RUN-TIME CODE PARALLELIZATION USING OUT-OF-ORDER RENAMING WITH PRE-ALLOCATION OF PHYSICAL REGISTERS 审中-公开
    使用物理寄存器预分配的无序重新发送来实现运行时代码并行化

    公开(公告)号：WO2017072600A1

    公开(公告)日：2017-05-04

    申请号：PCT/IB2016/054706

    申请日：2016-08-04

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： TENNENHAUS, Omri ,  MANDLER, Alberto ,  MIZRAHI, Noam

    IPC: G06F9/38

    CPC classification number: G06F9/384 ,  G06F9/3838

    Abstract: A method includes processing a sequence of instructions of program code that are specified using one or more architectural registers, by a hardware -implemented pipeline that renames the architectural registers in the instructions so as to produce operations specified using one or more physical registers (50), At least first and second segments of the sequence of instructions are selected, wherein the second segment occurs later in the sequence than the first segment. One or more of the architectural registers in the instructions of the second segment are renamed, before completing renaming the architectural registers in the instructions of the first segment, by pre-allocating one or more of the physical registers to one or more of the architectural registers.

    Abstract translation: 一种方法包括通过硬件实现的流水线来处理由一个或多个体系结构寄存器指定的程序代码的指令序列，该硬件实现的流水线重命名指令中的体系结构寄存器以便产生使用一个或多个体系结构寄存器 一个或多个物理寄存器（50），选择指令序列的至少第一和第二段，其中第二段在序列中比第一段晚。 在完成对第一段的指令中的架构寄存器的重命名之前，通过将一个或多个物理寄存器预先分配给一个或多个架构寄存器来重命名第二段的指令中的一个或多个架构寄存器

    PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES BASED ON PREMONITORING
    6.
    发明申请
    PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES BASED ON PREMONITORING 审中-公开
    基于预警的指令序列并行执行

    公开(公告)号：WO2016156955A1

    公开(公告)日：2016-10-06

    申请号：PCT/IB2015/059469

    申请日：2015-12-09

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： MIZRAHI, Noam ,  MANDLER, Alberto ,  KOREN, Shay ,  FRIEDMANN, Jonathan

    IPC: G06F9/38

    CPC classification number: G06F9/3851

    Abstract: A method includes, in a processor (20) that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.

    Abstract translation: 一种方法包括在处理程序代码指令的处理器（20）中，通过第一硬件线程处理一个或多个指令。 在检测到已经为第一线程获取定义为并行化点的指令时，调用第二硬件线程以至少部分地与第一硬件线程对指令的处理并行地处理指令中的至少一个。

    RUN-TIME CODE PARALLELIZATION WITH APPROXIMATE MONITORING OF INSTRUCTION SEQUENCES
    7.
    发明申请
    RUN-TIME CODE PARALLELIZATION WITH APPROXIMATE MONITORING OF INSTRUCTION SEQUENCES 审中-公开
    运行时代码与指令序列的大量监视并行

    公开(公告)号：WO2016139520A1

    公开(公告)日：2016-09-09

    申请号：PCT/IB2015/059468

    申请日：2015-12-09

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： MIZRAHI, Noam ,  MANDLER, Alberto ,  KOREN, Shay ,  FRIEDMANN, Jonathan

    IPC: G06F9/38

    CPC classification number: G06F11/3024 ,  G06F8/452 ,  G06F8/456 ,  G06F9/48 ,  G06F11/3404

    Abstract: A method includes, in a processor (20) that executes instructions of program code, identifying a region of the code containing one or more segments of the instructions that are at least partially repetitive. The instructions in the region are monitored, and an approximate specification of register access by the monitored instructions is constructed for the region. Execution of the segments in the region is parallelized using the specification.

    Abstract translation: 一种方法包括在执行程序代码的指令的处理器（20）中，识别包含至少部分重复的指令的一个或多个段的代码的区域。 监视该区域中的指令，并为该区域构建受监视指令的寄存器访问的近似规范。 使用规范并行执行区域中的段。

    RUN-TIME CODE PARALLELIZATION WITH CONTINUOUS MONITORING OF REPETITIVE INSTRUCTION SEQUENCES
    10.
    发明申请
    RUN-TIME CODE PARALLELIZATION WITH CONTINUOUS MONITORING OF REPETITIVE INSTRUCTION SEQUENCES 审中-公开
    连续监视重复指示序列的运行时代码并行化

    公开(公告)号：WO2016103092A1

    公开(公告)日：2016-06-30

    申请号：PCT/IB2015/059470

    申请日：2015-12-09

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： MIZRAHI, Noam ,  MANDLER, Alberto ,  KOREN, Shay ,  FRIEDMANN, Jonathan

    IPC: G06F9/38

    CPC classification number: G06F9/3851 ,  G06F9/381 ,  G06F9/45525 ,  G06F9/46

    Abstract: A method includes, in a processor (20) that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.

    Abstract translation: 一种方法包括在执行程序代码的指令的处理器（20）中监视遍历流程控制跟踪的指令的重复序列的指令，以便构建被监视指令的寄存器访问的规范。 基于该规范，调用多个硬件线程以至少部分地并行地执行重复指令序列的相应段。 在执行期间，至少一个段中的指令的监视继续。

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