公开(公告)号：WO1984004184A1

公开(公告)日：1984-10-25

申请号：PCT/US1984000558

申请日：1984-04-12

Applicant: CONVERGENT TECHNOLOGIES, INC.

Inventor： CONVERGENT TECHNOLOGIES, INC. ,  LOWENTHAL, Richard ,  MOMIROV, Milan ,  BURGER, John ,  SNYDER, Edwin

IPC: G06F01/04

CPC classification number: G06F11/10 ,  G06F1/04

Abstract: In a data processing system (10) which includes a central processing unit (22) capable of operating at a higher speed than memory device (20) associated therewith, method and apparatus provide for sensing and correcting errors generated in the memory device, particularly as a result of operation of the memory at speeds approaching design limits wherein errors may be introduced into the data. Specifically, clock stretching circuitry includes circuitry (36) which operate the central processing unit at a preselected clock rate, circuitry (42, 44, 46) which senses for data errors and circuitry (38) which introduces delays in the clocking of the central processing unit only in the presence of indicated data errors. The clock stretching interval permits error correcting circuitry (48) to correct identified bit errors in the data before the central processing unit accesses the data.

Abstract translation: 在包括能够以与其相关联的存储器件（20）更高速度运行的中央处理单元（22）的数据处理系统（10）中，方法和装置提供用于感测和校正在存储器件中产生的错误，特别是 这是在接近设计限制的速度下操作存储器的结果，其中错误可能被引入到数据中。 具体地，时钟延伸电路包括以预选的时钟速率操作中央处理单元的电路（36），其感测数据错误的电路（42,44,46）和引入中央处理时钟延迟的电路（38） 仅在存在指示的数据错误的情况下进行。 时钟延伸间隔允许纠错电路（48）在中央处理单元访问数据之前校正数据中的识别的位错误。