公开(公告)号：WO1993005466A1

公开(公告)日：1993-03-18

申请号：PCT/JP1992001130

申请日：1992-09-04

Applicant: SEIKO EPSON CORPORATION ,  TSUKAMOTO, Takashi

Inventor： SEIKO EPSON CORPORATION

IPC: G06F01/04

CPC classification number: H03L3/00 ,  H03K3/0307

Abstract: An oscillator provided with oscillation amplification means equipped with a plurality of oscillation inverters, for amplifying an original oscillation signal supplied from outside and outputting the amplified signal, selection means for generating a selection signal for selectively driving any of a plurality of oscillation inverters, amplification detection means for detecting output amplitude of the oscillation inverter driven in accordance with the selection signal, and generating a detection signal corresponding to the output amplitude, and oscillation indication means for designating the oscillation inverter to be selected on the basis of the detection signal. The oscillation indication means generates a selection indication signal for designating any of a plurality of oscillation inverters in accordance with the detection signal, and the selection means generates the selection signal corresponding to this selection indication signal. Since only the oscillation inverter equipped with a minimum necessary amplification capacity for continuing oscillation is always driven, excessive power consumption is much more restricted than in the prior art, and the oscillator has extremely low power consumption.

Abstract translation: 具有振荡放大装置的振荡器，配有多个振荡反相器，用于放大从外部提供的原始振荡信号并输出​​放大的信号;选择装置，用于产生用于选择性地驱动多个振荡反相器中的任何一个的放大检测 用于检测根据选择信号驱动的振荡反相器的输出振幅的装置，以及产生与输出振幅相对应的检测信号;以及振荡指示装置，用于基于检测信号指定要选择的振荡反相器。 振荡指示装置根据检测信号产生用于指定多个振荡反相器中的任一个的选择指示信号，并且选择装置产生与该选择指示信号对应的选择信号。 由于只有具有持续振荡的最小必要放大容量的振荡逆变器总是被驱动，因此与现有技术相比，过多的功耗受到限制，并且振荡器具有极低的功耗。

公开(公告)号：WO1992000558A2

公开(公告)日：1992-01-09

申请号：PCT/US1991004648

申请日：1991-06-28

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  KOKER, Gregory, T. ,  TSANG, Steven, T.

IPC: G06F01/04

CPC classification number: G06F1/10 ,  G06F1/06 ,  H03D13/004 ,  H03K5/13 ,  H03K5/26 ,  H03L7/0812 ,  H03L7/0895 ,  H03L7/0896

Abstract: A phase detector circuit is provided for correction of operation of a synchronous delay line clock generator. The phase detector includes multiple edge detectors (144, 146, 148). The multiple edge detectors provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding presence or absence of any phase error of less than 360 DEG , if the phase position of the delay line output signal is off by an integral multiple of 360 DEG . Multiple taps (TAP 2, TAP 9, TAP 14), from daisy-chained or series-connected delay line elements are provided to the multiple edge detectors. The multiple edge detectors compare the edge produced by each such tap against one division of a divided clock signal. Apparatus and method are provided for saving a control signal for a signal-controlled system. A control signal is provided to a multiplexer, which normally produces that control signal. That control signal is digitized and stored by a storage device. The output of the storage device is provided both to the multiplexer and to a comparator. The comparator also receives the output of the multiplexer, and compares the output of the storage device and the multiplexer. The comparator provides a signal to the storage device to increment or decrement the storage device.

Abstract translation: 提供了相位检测器电路，用于校正同步延迟线时钟发生器的操作。 相位检测器包括多个边缘检测器（144,146,148）。 如果延迟线输出信号的相位位置为0°，则多边缘检测器可以将相位检测器的其余部分对同步延迟线输出进行任何校正动作的覆盖，尽管存在或不存在小于360°的任何相位误差 360度的整数倍。 将多个抽头（TAP 2，TAP 9，TAP 14）从菊花链或串联连接的延迟线元件提供给多个边缘检测器。 多边缘检测器将由每个这样的抽头产生的边缘与划分的时钟信号的一个划分进行比较。 提供了用于保存用于信号控制系统的控制信号的装置和方法。 控制信号被提供给多路复用器，其通常产生该控制信号。 该控制信号由存储装置数字化并存储。 存储设备的输出提供给多路复用器和比较器。 比较器还接收多路复用器的输出，并比较存储设备和多路复用器的输出。 比较器向存储设备提供信号以使存储设备递增或递减。

公开(公告)号：WO1986000432A1

公开(公告)日：1986-01-16

申请号：PCT/US1985000761

申请日：1985-04-24

Applicant: AMERICAN TELEPHONE & TELEGRAPH COMPANY

Inventor： AMERICAN TELEPHONE & TELEGRAPH COMPANY ,  SHEETS, Laurence, LeRoy

IPC: G06F01/04

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  Y02D10/126

Abstract: The microprocessor unit of a system implemented using metal-oxide-silicon (MOS) technology, is driven by a variable-frequency clock. The microprocessor controls the clock frequency based on the present rate of required microprocessor activity. By driving the microprocessor unit at a lower clock frequency when such activity rate is low, the energy dissipated by the microprocessor unit is reduced due to the MOS power-frequency characteristic.

公开(公告)号：WO1994008284A1

公开(公告)日：1994-04-14

申请号：PCT/US1993001358

申请日：1993-02-15

Applicant: DAVIS, Michael, H. ,  ROSCH, Winn, L.

Inventor： DAVIS, Michael, H.

IPC: G06F01/04

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3228 ,  G06F11/3423 ,  G06F11/3466 ,  Y02D10/126 ,  Y02D10/34

Abstract: A process and apparatus for preparing said process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator (18) governing the logical operation of the microprocessor (10) during periods of use in which system performance is not critical. In one embodiment of apparatus the microprocessor (10) is controlled by a monitor circuit operable with the microprocessor and operated by the variable frequency oscillator. In another embodiment a hardware monitor circuit is utilized and which tracks microprocessor instructions to determine periods of use when performance is not critical. The shift in oscillator speed is mediated by a flip-flop latch circuit (28) connected between one or more clock oscillators and the oscillator input of the controlled microprocessor.

Abstract translation: 一种用于通过在系统性能不是关键的使用期间减小控制微处理器（10）的逻辑运行的振荡器（18）的频率来制备用于降低基于微处理器的设备的功耗的方法和装置。 在装置的一个实施例中，微处理器（10）由可由微处理器操作并由可变频率振荡器操作的监视器电路控制。 在另一个实施例中，使用硬件监视器电路，并且当性能不是关键时，跟踪微处理器指令来确定使用周期。 振荡器速度的移动由连接在一个或多个时钟振荡器和受控微处理器的振荡器输入之间的触发器锁存电路（28）介导。

公开(公告)号：WO1990002990A1

公开(公告)日：1990-03-22

申请号：PCT/US1989003938

申请日：1989-09-11

Applicant: SILICON GRAPHICS, INC.

Inventor： SILICON GRAPHICS, INC. ,  HANNAH, Marc, R.

IPC: G06F01/04

CPC classification number: G06T15/405

Abstract: A method for updating a single ported, pipelined Z-buffer (11) where the Z-buffer is updated only after determining the beginning and ending location of a contiguous group of pixels requiring up dating in the Z-buffer. This allows parallel operations in a graphics architecture that utilizes a single ported Z-buffer memory.

公开(公告)号：WO1984004184A1

公开(公告)日：1984-10-25

申请号：PCT/US1984000558

申请日：1984-04-12

Applicant: CONVERGENT TECHNOLOGIES, INC.

Inventor： CONVERGENT TECHNOLOGIES, INC. ,  LOWENTHAL, Richard ,  MOMIROV, Milan ,  BURGER, John ,  SNYDER, Edwin

IPC: G06F01/04

CPC classification number: G06F11/10 ,  G06F1/04

Abstract: In a data processing system (10) which includes a central processing unit (22) capable of operating at a higher speed than memory device (20) associated therewith, method and apparatus provide for sensing and correcting errors generated in the memory device, particularly as a result of operation of the memory at speeds approaching design limits wherein errors may be introduced into the data. Specifically, clock stretching circuitry includes circuitry (36) which operate the central processing unit at a preselected clock rate, circuitry (42, 44, 46) which senses for data errors and circuitry (38) which introduces delays in the clocking of the central processing unit only in the presence of indicated data errors. The clock stretching interval permits error correcting circuitry (48) to correct identified bit errors in the data before the central processing unit accesses the data.

Abstract translation: 在包括能够以与其相关联的存储器件（20）更高速度运行的中央处理单元（22）的数据处理系统（10）中，方法和装置提供用于感测和校正在存储器件中产生的错误，特别是 这是在接近设计限制的速度下操作存储器的结果，其中错误可能被引入到数据中。 具体地，时钟延伸电路包括以预选的时钟速率操作中央处理单元的电路（36），其感测数据错误的电路（42,44,46）和引入中央处理时钟延迟的电路（38） 仅在存在指示的数据错误的情况下进行。 时钟延伸间隔允许纠错电路（48）在中央处理单元访问数据之前校正数据中的识别的位错误。

公开(公告)号：WO1998013742A1

公开(公告)日：1998-04-02

申请号：PCT/JP1997003397

申请日：1997-09-24

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  YAMAMOTO, Akira ,  SAKIYAMA, Shiro ,  NAKAHIRA, Hiroyuki ,  FUKUDA, Masaru ,  MATSUZAWA, Akira ,  DOSHO, Shiro ,  YAMAMOTO, Shinichi

Inventor： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

IPC: G06F01/04

CPC classification number: G01R23/06 ,  G06F1/3203 ,  Y02D10/126

Abstract: A frequency-voltage conversion circuit (21) is adapted to receive clock (CLK) as an input, and provide as an output a voltage (IVdd) corresponding to the frequency of the clock (CLK). The input/output characteristics of the frequency-voltage conversion circuit (21) are so adjusted that they substantially agree with given input/output characteristics.

Abstract translation: 频率电压转换电路（21）适于接收时钟（CLK）作为输入，并提供与时钟（CLK）的频率对应的电压（IVdd）作为输出。 频率电压转换电路（21）的输入/输出特性如此调节，使得它们基本上符合给定的输入/输出特性。

公开(公告)号：WO1997022916A1

公开(公告)日：1997-06-26

申请号：PCT/US1996018849

申请日：1996-11-21

Applicant: CREDENCE SYSTEMS CORPORATION

Inventor： CREDENCE SYSTEMS CORPORATION ,  LESMEISTER, Gary, J. ,  BEDELL, Daniel, J.

IPC: G06F01/04

CPC classification number: G01R31/2851 ,  G01R31/31813 ,  G01R31/31907 ,  G01R31/3191 ,  G01R31/31921 ,  G01R31/31922 ,  G06F1/025 ,  G06F1/04

Abstract: A timing signal generator (10) includes a voltage controlled oscillator (VCO) (14), a logic circuit (21), N set circuits (19), N reset circuits (20) and a bistable latch circuit (23). The VCO produces a set of N reference signals (T1-TN) frequency locked to a reference clock signal (T1) and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit (21) asserts ones of N set signals (SE1-SEN) and N reset signals (RE1-REN) selected by input control words. The timing of leading and trailing edges of pulses of the output timing signal (26) may be controlled with a resolution that is 1/Nth of the period of the reference clock by supplying an appropriate control word sequence to the logic circuit.

Abstract translation: 定时信号发生器（10）包括压控振荡器（VCO）（14），逻辑电路（21），N组电路（19），N个复位电路（20）和双稳态锁存电路（23）。 VCO产生频率锁定到参考时钟信号（T1）的N个参考信号（T1-TN）的集合并且相位分布，以将参考时钟周期均匀地分解为N个间隔。 逻辑电路（21）断言由输入控制字选择的N个置位信号（SE1-SEN）和N个复位信号（RE1-REN）中的一个。 输出定时信号（26）的脉冲的前沿和后沿的定时可以通过向逻辑电路提供适当的控制字序列，以基准时钟周期的1 / N的分辨率来控制。

公开(公告)号：WO1996017288A1

公开(公告)日：1996-06-06

申请号：PCT/US1995016383

申请日：1995-11-29

Applicant: ELONEX TECHNOLOGIES, INC.

Inventor： ELONEX TECHNOLOGIES, INC. ,  DORNIER, Pascal

IPC: G06F01/04

CPC classification number: G11C7/22

Abstract: Timing is set for DRAM memory access in a computer by polling the DRAM memory banks (11), calculating capacitive load by accessing a prestored table of capacitive load versus DRAM size (fig. 3), and assigning wait states according to calculated capacitive load by accessing a prestored formula. In one embodiment, wait states are assigned in increasing increments for increasing total capacitive load. In an alternative embodiment, timing is assigned bank by bank. Control routines are preferably a part of a system BIOS (14).

Abstract translation: 通过轮询DRAM存储器组（11），通过访问容量负载与DRAM大小的预存储表（图3）来计算容量负载，并根据计算出的容性负载来分配等待状态，为计算机中的DRAM存储器访问设置时序 访问预先存储的公式。 在一个实施例中，等待状态以递增的增量被分配以增加总容性负载。 在替代实施例中，按银行划分时间。 控制例程优选地是系统BIOS（14）的一部分。

公开(公告)号：WO1987001479A1

公开(公告)日：1987-03-12

申请号：PCT/JP1986000450

申请日：1986-09-04

Applicant: FUJITSU LIMITED ,  YOSHIMURA, Tatsuro

Inventor： FUJITSU LIMITED

IPC: G06F01/04

CPC classification number: G06F1/10

Abstract: A logic circuit equipped with a scan in/out means that is provided with n+p specific scan in/out latch circuits. A first delay means which selectively generates input clocks as delay clock signals of a maximum of m = 2n steps according to selection signals of n bits, is connected in cascade with a second delay means which selectively generates input clock signals as delay clock signals of a minimum step of 1/2p times as small as the width of a minimum step of the clock signals by said first delay means, according to selection signals of p bits. By setting selection data to said n+p scan in/out latch circuits, any delay clock signal can be obtained that is delayed by a given 1/2p step relative to the input clock signal.