公开(公告)号：WO1984004190A1

公开(公告)日：1984-10-25

申请号：PCT/US1984000557

申请日：1984-04-12

Applicant: CONVERGENT TECHNOLOGIES, INC.

Inventor： CONVERGENT TECHNOLOGIES, INC. ,  LOWENTHAL, Richard ,  HUIE, Jonathan ,  MOMIROV, Milan ,  WEGBREIT, Ben ,  CLINE, David ,  BURGER, John, P.

IPC: G06F15/16

CPC classification number: G06F15/17

Abstract: A multi-computer computer architecture that provides a plurality of specialized function, independent asynchronous parallel processors (11-14). Each processor has a discrete and independent operating system; the processors are interconnected for transparent interprocessor communication at an operating system level across an asynchronous parallel bus (10). Each of said processors includes a central processing unit (18) and a memory storage (17). The processors pass messages to each other by placing the message in a receiving processor's memory store. The receiving processor is notified of the presence of the message by a doorbell interrupt, received from the message passing processor. The individual processors are intercoupled via a plurality of connecting slots, said slots defining an enclosure (15) which forms an independent, functional multi-computer unit. A plurality of enclosures (15, 16) may be transparently interconnected to define a multi-computer system. In this way, a computer architecture is provided that is expandable from a minicomputer configuration to a large main frame configuration as application and use requires.

Abstract translation: 提供多个专用功能的多计算机计算机体系结构，独立的异步并行处理器（11-14）。 每个处理器都有独立的独立操作系统; 处理器被互连以用于在跨异步并行总线（10）的操作系统级别进行透明的处理器间通信。 每个所述处理器包括中央处理单元（18）和存储器存储器（17）。 处理器通过将消息放置在接收处理器的存储器中来彼此传递消息。 通过从消息传递处理器接收到的门铃中断来向接收处理器通知消息的存在。 各个处理器经由多个连接槽相互配合，所述槽限定形成独立的功能多计算机单元的机壳（15）。 多个外壳（15,16）可以透明地互连以限定多计算机系统。 以这种方式，提供了一种计算机架构，其可以从应用和使用所需的小型计算机配置扩展到大的主框架配置。

公开(公告)号：WO1984004184A1

公开(公告)日：1984-10-25

申请号：PCT/US1984000558

申请日：1984-04-12

Applicant: CONVERGENT TECHNOLOGIES, INC.

Inventor： CONVERGENT TECHNOLOGIES, INC. ,  LOWENTHAL, Richard ,  MOMIROV, Milan ,  BURGER, John ,  SNYDER, Edwin

IPC: G06F01/04

CPC classification number: G06F11/10 ,  G06F1/04

Abstract: In a data processing system (10) which includes a central processing unit (22) capable of operating at a higher speed than memory device (20) associated therewith, method and apparatus provide for sensing and correcting errors generated in the memory device, particularly as a result of operation of the memory at speeds approaching design limits wherein errors may be introduced into the data. Specifically, clock stretching circuitry includes circuitry (36) which operate the central processing unit at a preselected clock rate, circuitry (42, 44, 46) which senses for data errors and circuitry (38) which introduces delays in the clocking of the central processing unit only in the presence of indicated data errors. The clock stretching interval permits error correcting circuitry (48) to correct identified bit errors in the data before the central processing unit accesses the data.

Abstract translation: 在包括能够以与其相关联的存储器件（20）更高速度运行的中央处理单元（22）的数据处理系统（10）中，方法和装置提供用于感测和校正在存储器件中产生的错误，特别是 这是在接近设计限制的速度下操作存储器的结果，其中错误可能被引入到数据中。 具体地，时钟延伸电路包括以预选的时钟速率操作中央处理单元的电路（36），其感测数据错误的电路（42,44,46）和引入中央处理时钟延迟的电路（38） 仅在存在指示的数据错误的情况下进行。 时钟延伸间隔允许纠错电路（48）在中央处理单元访问数据之前校正数据中的识别的位错误。