公开(公告)号：WO1984004185A1

公开(公告)日：1984-10-25

申请号：PCT/US1984000556

申请日：1984-04-12

Applicant: CONVERGENT TECHNOLOGIES, INC.

Inventor： CONVERGENT TECHNOLOGIES, INC. ,  BURGER, John, P.

IPC: G06F03/00

CPC classification number: G06F13/4045 ,  G06F13/37 ,  G06F13/4031 ,  H05K1/14

Abstract: Method and apparatus for allowing multiple enclosures (10) to be connected so that their respective motherboards (15) together define a single bus. Systemwide arbitration is carried out asynchronously on an enclosure basis while arbitration within each enclosure occurs synchronously. A bus repeater (20, 25, 25') is provided at each of the upstream and downstream ends of each enclosure's motherboard. The upstream bus repeater (20) in a given enclosure is coupled by a flexible connector cable (30) to the downstream bus repeater (25, 25') in the enclosure immediately upstream. One of the bus repeaters (say the upstream one) has the status as master or arbiter while the other has a status of a slave. The connector cables have two sets of lines (32, 35), thereby allowing the bus repeaters to pass two basic types of signals: (a) bused signals (address, data) which are made available to the relevant unit boards; and (b) private signals which are passed only to the bus repeaters. The set of private signals comprises two subsets (i) downstream bound, and (ii) upstream bound, each subset of which includes request, busy, grant, and arbitrate signals. Within each enclosure, the bus repeaters monitor the local bus request and bus busy lines, and logically combine them with the upstream bound and downstream bound private request and busy signals.

公开(公告)号：WO1984004190A1

公开(公告)日：1984-10-25

申请号：PCT/US1984000557

申请日：1984-04-12

Applicant: CONVERGENT TECHNOLOGIES, INC.

Inventor： CONVERGENT TECHNOLOGIES, INC. ,  LOWENTHAL, Richard ,  HUIE, Jonathan ,  MOMIROV, Milan ,  WEGBREIT, Ben ,  CLINE, David ,  BURGER, John, P.

IPC: G06F15/16

CPC classification number: G06F15/17

Abstract: A multi-computer computer architecture that provides a plurality of specialized function, independent asynchronous parallel processors (11-14). Each processor has a discrete and independent operating system; the processors are interconnected for transparent interprocessor communication at an operating system level across an asynchronous parallel bus (10). Each of said processors includes a central processing unit (18) and a memory storage (17). The processors pass messages to each other by placing the message in a receiving processor's memory store. The receiving processor is notified of the presence of the message by a doorbell interrupt, received from the message passing processor. The individual processors are intercoupled via a plurality of connecting slots, said slots defining an enclosure (15) which forms an independent, functional multi-computer unit. A plurality of enclosures (15, 16) may be transparently interconnected to define a multi-computer system. In this way, a computer architecture is provided that is expandable from a minicomputer configuration to a large main frame configuration as application and use requires.

Abstract translation: 提供多个专用功能的多计算机计算机体系结构，独立的异步并行处理器（11-14）。 每个处理器都有独立的独立操作系统; 处理器被互连以用于在跨异步并行总线（10）的操作系统级别进行透明的处理器间通信。 每个所述处理器包括中央处理单元（18）和存储器存储器（17）。 处理器通过将消息放置在接收处理器的存储器中来彼此传递消息。 通过从消息传递处理器接收到的门铃中断来向接收处理器通知消息的存在。 各个处理器经由多个连接槽相互配合，所述槽限定形成独立的功能多计算机单元的机壳（15）。 多个外壳（15,16）可以透明地互连以限定多计算机系统。 以这种方式，提供了一种计算机架构，其可以从应用和使用所需的小型计算机配置扩展到大的主框架配置。