公开(公告)号：WO1993004462A1

公开(公告)日：1993-03-04

申请号：PCT/US1992007055

申请日：1992-08-21

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： DIGITAL EQUIPMENT CORPORATION ,  MEINERTH, Kim ,  BOUCHARD, Joseph ,  CASE, Colyn ,  CROUSE, Robert ,  FANNING, Blaise ,  FIELDING, Kevin ,  FRANKLIN, Chris ,  GAMACHE, Rodney ,  IRWIN, John ,  KIRK, John ,  KRISHNASWAMI, Srinivasan ,  LORD, George ,  MASUCCI, Agnes, M. ,  MOEZZI, Ali ,  PAYSON, Christopher, J. ,  SCOTT, George

IPC: G09G05/40

CPC classification number: G09G5/393 ,  G06F9/3879 ,  G06F12/0831 ,  G06F12/1027 ,  G09G5/06 ,  G09G5/08 ,  G09G5/363 ,  G09G2310/04 ,  G09G2360/121 ,  G09G2360/123 ,  G09G2360/126

Abstract: A low cost, high performance computer graphics system. A graphics processor, capable of making memory requests is connected to a memory control unit, which controls a memory bus. Both main memory and a frame buffer memory are attached to the memory bus, thereby giving the graphics processor the capability of writing to either main memory or to the frame buffer memory. The disclosure further describes a computer graphics system, having a duplicate cache tag store accessible by the graphics system without generating traffic on the system bus; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a residue buffer for the temporary storage of memory transmissions not immediately usable by the graphics processor; having a "short circuit" feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.

Abstract translation: 低成本，高性能的计算机图形系统。 能够进行存储器请求的图形处理器连接到控制存储器总线的存储器控​​制单元。 主存储器和帧缓冲存储器都附加到存储器总线，从而给图形处理器写入主存储器或帧缓冲存储器的能力。 本公开还描述了一种计算机图形系统，其具有由图形系统可访问的重复高速缓存标签存储器，而不在系统总线上产生业务; 在主存储器中具有用于临时存储图形命令的FIFO命令缓冲器; 具有用于临时存储图形处理器不能立即使用的存储器传输的残留缓冲器; 具有用于以最小数量的步骤将图形命令路由到命令处理器的“短路”特征; 具有能够将光标图案信息存储在主存储器中并从主存储器检索光标图案信息的光标控制系统; 具有可重配置以携带除光标信息之外的信息的光标总线; 并具有不包含定时或光标控制电路的帧缓冲器模块。