Abstract:
A storage pixel sensor disposed on a semiconductor substrate comprises a photodiode having a first terminal coupled to a first potential and a second terminal. A barrier transistor has a first terminal coupled to the second terminal of the photodiode, a second terminal and a control gate coupled to a barrier set voltage. A reset transistor has a first terminal coupled to the second terminal of the barrier transistor, a second terminal coupled to a reset reference potential that reverse biases the photodiode, and a control gate coupled to a source of a RESET signal. A photocharge integration node is coupled to said second terminal of said barrier transistor. The photocharge integration node comprises the control gate of a first source-follower transistor. The first source-follower transistor is coupled to a source of bias current and has an output. A capacitive storage node is coupled to the output of the first source-follower transistor and comprises the control gate of a second source-follower transistor having an output. An exposure transistor is coupled between the output of the first source-follower transistor and a global current-summing node and has a control gate coupled to a saturation level voltage.
Abstract:
A digital pixel sensor is formed on a semiconductor substrate and comprises a phototransducer responsive to light for providing an analog output signal that is a function of an incident amount of light. A comparator is configured to compare the analog output signal and a ramp reference signal. A plurality of n DRAM cells are configured to store an at least n-bit digital signal in response to the output of the comparator. An array of digital pixel sensors is also disclosed.
Abstract:
A digital camera comprises a light-tight housing. At least one solid-state array image sensor is disposed in the housing. A lens is optically coupled to the solid-state array image sensor through the housing. A viewing screen is coupled to the solid-state array image sensor for viewing an image sensed by the solid-state array image sensor. A user-operated pointing device is used to select a point anywhere on the image. Circuitry associated with the solid state array image sensor is responsive to the pointing device for presenting on the viewing screen an area associated with the point on the image, the area being magnified and having higher resolution with respect to the remainder of the image.
Abstract:
A storage pixel sensor disposed on a semiconductor substrate comprises a photodiode having a first terminal coupled to a first potential and a second terminal. A barrier transistor has a first terminal coupled to the second terminal of the photodiode, a second terminal and a control gate coupled to a barrier set voltage. A reset transistor has a first terminal coupled to the second terminal of the barrier transistor, a second terminal coupled to a reset reference potential that reverse biases the photodiode, and a control gate coupled to a source of a RESET signal. A photocharge integration node is coupled to said second terminal of said barrier transistor. The photocharge integration node comprises the control gate of a first source-follower transistor. The first source-follower transistor is coupled to a source of bias current and has an output. A capacitive storage node is coupled to the output of the first source-follower transistor and comprises the control gate of a second source-follower transistor having an output. An exposure transistor is coupled between the output of the first source-follower transistor and a global current-summing node and has a control gate coupled to a saturation level voltage.
Abstract:
Active pixel sensor array with bootstrap amplification, comprising a plurality of active pixels arranged in rows and columns, wherein each active pixel comprises a photodiode (12), a reset transistor (14), a source follower transistor (16), and a row select transistor (18); it may additionally comprise a transfer transistor (32). Each row of active pixels comprises a separate source, follower drain row line (Vd), coupled to the drains of the source-follower transistors (16) within said row. The potential of the drain row line is set relatively low during the integration period, and is set relatively high during charge-readout, in order to increase the read-out voltage.
Abstract:
A pixel sensor array structure which reduces the amount of striped fixed pattern noise includes a plurality of pixel sensors arranged in an array; a column in the array, a plurality of load devices, each load device coupled to one of the column lines and to a column reset reference potential; a plurality of column select switches, the common line coupled to the column select switches and to a buffer amplifier. A unity-gain buffer amplifier may be coupled to the common line and to a driven shield, which acts to reduce the effective capacitance of the common line. The column select switches transistors may be designed with an annular layout to reduce the capacitance they add to the common line. The load devices may be designed with a relatively large length and width to minimize variations in their bias currents. A two-tap FIR filter may be coupled to the array amplifier to correct pixel values which may be blurred when fast multiplexing is used.