公开(公告)号：WO2017145197A1

公开(公告)日：2017-08-31

申请号：PCT/JP2016/001056

申请日：2016-02-26

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： YANG, Wentao ,  SIN, Johnny Kin On ,  ONOZAWA, Yuichi

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L21/32131 ,  H01L21/32139 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/401 ,  H01L29/404 ,  H01L29/408

Abstract: At edge termination region (12), a trench (22) is disposed near an interface of an active region (11). Inside the trench (22), an embedded insulating film (23) is embedded, and inside the embedded insulating film (23), a FP (45) long in a direction of depth is disposed. The FP (45) curves outwardly away from an inner side wall (22a) of the trench (22) as a depth from a base front surface increases. At least near a bottom end of the FP (45), a distance (w3) between the FP (45) and the inner side wall (22a) of trench (22) is greater than a width (w2) of the groove (24). The FP (45) is connected to a front surface electrode (4) that extends on the embedded insulating film (23). As a result, breakdown voltage can be enhanced, adverse effects of the surface charge can be reduced, and chip size can be further reduced.

Abstract translation: 在边缘终止区（12）处，沟槽（22）设置在有源区（11）的界面附近。 在沟槽（22）内埋入嵌入绝缘膜（23），在埋入绝缘膜（23）的内部配置深度方向较长的FP（45）。 随着距基部前表面的深度增加，FP（45）从沟槽（22）的内侧壁（22a）向外弯曲。 至少在FP（45）的底端附近，FP（45）与沟槽（22）的内侧壁（22a）之间的距离（w3）大于沟槽（24）的宽度（w2） ）。 FP（45）连接到在嵌入绝缘膜（23）上延伸的前表面电极（4）。 结果，可以增强击穿电压，可以降低表面电荷的不利影响，并且可以进一步减小芯片尺寸。

公开(公告)号：WO2023058209A1

公开(公告)日：2023-04-13

申请号：PCT/JP2021/037253

申请日：2021-10-07

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： TSUJI, Takashi ,  ONOZAWA, Yuichi ,  FUJISHIMA, Naoto ,  HUANG, Linhua ,  SIN, Johnny Kin On

IPC: H01L29/78 ,  H01L29/12 ,  H01L29/739 ,  H01L21/336

Abstract: A gate insulating film (8) has a multilayer structure including a SiO2 film (8a), a LaAlO3 film (8b), and an Al2O3 film (8c) that are sequentially stacked, relative permittivity of the gate insulating film being optimized by the LaAlO3 film (8b). In forming the LaAlO3 film (8b) constituting the gate insulating film (8), a La2O3 film and an Al2O3 film are alternately deposited repeatedly using an ALD method. At this time, the La2O3 film is deposited first, whereby during a POA performed thereafter, a sub-oxide of the surface of the SiO2 film is removed by a cleaning effect of lanthanum atoms in the La2O3 film. A temperature of this POA is suitably set in a range from 700 degrees C to less than 900 degrees C. As a result, without disposing, near a bottom of a trench (7) embedded with the MOS gate, a p+-type region for mitigating electric field, electric field applied to the gate insulating film (8) at the bottom of the trench (7) can be mitigated, and reliability of the gate insulating film (8) can be ensured.