公开(公告)号：WO2023036472A1

公开(公告)日：2023-03-16

申请号：PCT/EP2022/055105

申请日：2022-03-01

Applicant: GRAPHCORE LIMITED

Inventor： ALEXANDER, Alan ,  OSBORNE, Richard ,  CHESNEY, Sam ,  ANDREWS, Edward

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: For certain applications, parts of the application data held in memory of a processing device (e.g. that are produced as a result of operations performed by the execution unit) are arranged in regular repeating patterns in the memory, and therefore, the execution unit may set up a suitable striding pattern for use by a send engine. The send engine accesses the memory at locations in accordance with the configured striding pattern so as to access a plurality of items of data that are arranged together in a regular pattern. In a similar manner as done for sends, the execution may set up a striding pattern for use by a receive engine. The receive engine, upon receiving a plurality of items of data, causes those items of data to be stored at locations in the memory, as determined in accordance with the configured striding pattern.

公开(公告)号：WO2023285304A1

公开(公告)日：2023-01-19

申请号：PCT/EP2022/069053

申请日：2022-07-08

Applicant: GRAPHCORE LIMITED

Inventor： OSBORNE, Richard ,  FELIX, Stephen

IPC: G06F9/52 ,  G06F15/173

Abstract: A set of configurable sync groupings (which may be referred to as sync zones) are defined. Any of the processors may belong to any of the sync zones. Each of the processor comprises a register indicating to which of the sync zones it belongs. If a processor does not belong to a sync zone, it continually asserts a sync request for that sync zone to the sync controller. If a processor does belong to a sync zone, it will only assert its sync request for that sync zone upon arriving at a synchronisation point for that sync zone indicated in its compiled code set.

公开(公告)号：WO2023285113A1

公开(公告)日：2023-01-19

申请号：PCT/EP2022/067456

申请日：2022-06-24

Applicant: GRAPHCORE LIMITED

Inventor： WILKINSON, Daniel ,  ALEXANDER, Alan ,  FELIX, Stephen ,  OSBORNE, Richard ,  KNOWLES, Simon ,  LACEY, David ,  HUUSE, Lars Paul

IPC: G06F9/52 ,  G06F15/173

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.