中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.015 seconds)

    MULTI-CLOCK CONTROL
    1.
    发明申请
    MULTI-CLOCK CONTROL 审中-公开

    公开(公告)号：WO2022012771A1

    公开(公告)日：2022-01-20

    申请号：PCT/EP2020/087564

    申请日：2020-12-22

    Applicant: GRAPHCORE LIMITED

    Inventor： CHAMBERS, Simon Douglas ,  FELIX, Stephen ,  KING, Ian Malcolm

    IPC: G06F1/06 ,  G06F1/08

    Abstract: Two clocks, a fast clock and a slow clock are provided for clocking a processing unit. A plurality of frequency settings, referred to as gears, are defined for the two clock. Each of these gears indicates a maximum frequency for the fast clock and a minimum frequency for the slow clock, such that the gap between the two frequencies may be kept to a manageable level so as to reduce transients upon switching between the two clocks. The system switches between the gears as required. In response to a determination to increase the frequency of the clock signal, a higher gear is selected at which the maximum and minimum frequencies defined for that gear are higher than the previous selected gear. Likewise, in response to a determination to decrease the frequency of the clock signal, a lower gear is selected, at which the maximum and minimum frequencies defined for that gear are lower than the previous selected gear.

    HARDWARE MODULE FOR CONVERTING NUMBERS
    2.
    发明申请
    HARDWARE MODULE FOR CONVERTING NUMBERS 审中-公开

    公开(公告)号：WO2020126124A1

    公开(公告)日：2020-06-25

    申请号：PCT/EP2019/066477

    申请日：2019-06-21

    Applicant: GRAPHCORE LIMITED

    Inventor： FELIX, Stephen ,  GORE, Mrudula

    IPC: G06F7/58

    Abstract: A hardware module comprising circuity configured to: store a sequence of n bits in a register of the hardware module; generate a signed integer comprising a magnitude component and a sign bit by: if the most significant bit of the sequence of n bits is equal to one: set each of the n-l of the most significant bits of the magnitude component to be equal to the corresponding bit of the n-1 least significant bits of the sequence of n bits; and set the sign bit to be zero; if the most significant bit of the sequence of n bits is equal to zero: set each of the n-l of the most significant bits of the magnitude component to be equal to the inverse of the corresponding bit of the n-1 least significant bits of the sequence of n bits; and set the sign bit to be one.

    REACTIVE DROOP LIMITER
    3.
    发明申请
    REACTIVE DROOP LIMITER 审中-公开

    公开(公告)号：WO2021129974A1

    公开(公告)日：2021-07-01

    申请号：PCT/EP2020/081632

    申请日：2020-11-10

    Applicant: GRAPHCORE LIMITED

    Inventor： FELIX, Stephen ,  WILKINSON, Daniel John Pelham

    IPC: H03K19/003 ,  G06F1/30 ,  G01R19/16552 ,  G06F1/08 ,  G06F1/305 ,  G06F1/3206 ,  G06F1/324 ,  G06F11/3058 ,  H03K19/00346 ,  H03K19/00369 ,  H03L7/1803

    Abstract: During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider (21) that is configured to receive an output (Fin) of a clock signal generator (4) (e.g. a phase locked loop) and produce an output signal (Fout) in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way, VDD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive VDD droop across the processor.

    SUBSCRIPTION TO SYNC ZONES
    4.
    发明申请
    SUBSCRIPTION TO SYNC ZONES 审中-公开

    公开(公告)号：WO2023285304A1

    公开(公告)日：2023-01-19

    申请号：PCT/EP2022/069053

    申请日：2022-07-08

    Applicant: GRAPHCORE LIMITED

    Inventor： OSBORNE, Richard ,  FELIX, Stephen

    IPC: G06F9/52 ,  G06F15/173

    Abstract: A set of configurable sync groupings (which may be referred to as sync zones) are defined. Any of the processors may belong to any of the sync zones. Each of the processor comprises a register indicating to which of the sync zones it belongs. If a processor does not belong to a sync zone, it continually asserts a sync request for that sync zone to the sync controller. If a processor does belong to a sync zone, it will only assert its sync request for that sync zone upon arriving at a synchronisation point for that sync zone indicated in its compiled code set.

    HOST PROXY ON GATEWAY
    7.
    发明申请
    HOST PROXY ON GATEWAY 审中-公开

    公开(公告)号：WO2020007738A1

    公开(公告)日：2020-01-09

    申请号：PCT/EP2019/067375

    申请日：2019-06-28

    Applicant: GRAPHCORE LIMITED

    Inventor： TØRUNDBAKKEN, Ola ,  WILKINSON, Daniel John Pelham ,  OSBORNE, Richard Luke Southwell ,  FELIX, Stephen ,  FYLES, Matthew David ,  MANULA, Brian ,  HØEG, Harald

    IPC: G06F13/40 ,  G06F13/42

    Abstract: A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host, the gateway enabling the transfer of batches of data to and from the subsystem at precompiled data exchange synchronisation points attained by the subsystem. The gateway is configured to: receive from a storage system data determined by the host to be processed by the subsystem; store a number of credits indicating the availability of data for transfer to the subsystem at each pre-compiled data exchange synchronisation point; receive a synchronisation request from the subsystem when it attains a data exchange synchronisation point; and in response to determining that the number of credits comprises a non-zero number of credits: transmit a synchronisation acknowledgment to the subsystem; and cause the received data to be transferred to the subsystem.

Patent Agency Ranking