公开(公告)号：WO2023285113A1

公开(公告)日：2023-01-19

申请号：PCT/EP2022/067456

申请日：2022-06-24

Applicant: GRAPHCORE LIMITED

Inventor： WILKINSON, Daniel ,  ALEXANDER, Alan ,  FELIX, Stephen ,  OSBORNE, Richard ,  KNOWLES, Simon ,  LACEY, David ,  HUUSE, Lars Paul

IPC: G06F9/52 ,  G06F15/173

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.