公开(公告)号：WO2015014304A1

公开(公告)日：2015-02-05

申请号：PCT/CN2014/083470

申请日：2014-07-31

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： JAEGER, Kent ,  CONNELL, Lawrence E. ,  MCCARTHY, Daniel P. ,  CREED, Brian T.

IPC: H03K3/012

CPC classification number: H03K5/15006

Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.

Abstract translation: 一种包括分频器的装置，包括以触发器配置耦合到第一锁存器的第一锁存器和第二锁存器，以及包括第一p沟道晶体管的输出电路，其中第一p沟道晶体管的栅极被配置 以接收时钟信号，第一n沟道晶体管，其中所述第一n沟道晶体管的栅极耦合到所述第一锁存器，与所述第一p沟道晶体管串联连接的第二n沟道晶体管和所述第一n沟道晶体管， 并且其中所述第二n沟道晶体管的栅极被配置为接收所述时钟信号;第二p沟道晶体管，其中所述第二p沟道晶体管的栅极被配置为接收所述时钟信号;以及第三p沟道晶体管， n沟道晶体管与第二p沟道晶体管和第二n沟道晶体管串联，其中输出电路被配置为产生一对同相参考信号。

公开(公告)号：WO2015014268A1

公开(公告)日：2015-02-05

申请号：PCT/CN2014/083205

申请日：2014-07-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： CONNELL, Lawrence E. ,  MCCARTHY, Daniel P. ,  CREED, Brian T.

IPC: G06G7/18

CPC classification number: H03K5/15006

Abstract: An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.

Abstract translation: 一种包括分频器的装置，包括：第一锁存器，被配置为接收第一时钟信号和第一时钟信号的补码，并产生第一锁存器第一输出;以及第二锁存器，以触发器配置耦合到第一锁存器， 包括p沟道晶体管的第一输出电路，其中p沟道晶体管的栅极被配置为接收第一时钟信号，以及n沟道晶体管，其中p沟道晶体管的漏极直接连接到 n沟道晶体管的漏极，其中n沟道晶体管的栅极被配置为接收第一锁存器第一输出，其中n沟道晶体管的源被配置为接收第一时钟信号的补码，并且其中 第一输出电路被配置为产生同相参考信号，以及第二输出电路，被配置为产生正交信号。