TRANSACTIONAL PROCESSING
    3.
    发明申请
    TRANSACTIONAL PROCESSING 审中-公开
    交易处理

    公开(公告)号:WO2013186721A3

    公开(公告)日:2014-05-30

    申请号:PCT/IB2013054812

    申请日:2013-06-12

    Applicant: IBM IBM UK

    CPC classification number: G06F9/467 G06F9/3004 G06F9/30087 G06F9/3834

    Abstract: A transaction is initiated via a transaction begin instruction. During execution of the transaction, the transaction may abort. If the transaction aborts, a determination is made as to the type of transaction. Based on the transaction being a first type of transaction, resuming execution at the transaction begin instruction, and based on the transaction being a second type, resuming execution at an instruction following the transaction begin instruction. Regardless of transaction type, resuming execution includes restoring one or more registers specified in the transaction begin instruction and discarding transactional stores. For one type of transaction, the nonconstrained transaction, the resuming includes storing information in a transaction diagnostic block.

    Abstract translation: 交易通过交易开始指令启动。 交易执行期间,交易可能会中止。 如果交易中止,则确定交易的类型。 基于事务是第一种类型的事务,在事务开始指令中恢复执行,并且基于该事务是第二类型,在事务开始指令之后的指令处恢复执行。 不管交易类型如何,恢复执行包括恢复在事务开始指令中指定的一个或多个寄存器,并丢弃事务存储。 对于一种类型的事务,非约束事务,恢复包括将信息存储在事务诊断块中。

    NEXT INSTRUCTION ACCESS INTENT INSTRUCTION
    4.
    发明申请
    NEXT INSTRUCTION ACCESS INTENT INSTRUCTION 审中-公开
    下一条指导访问指导

    公开(公告)号:WO2013186266A3

    公开(公告)日:2014-02-13

    申请号:PCT/EP2013062165

    申请日:2013-06-12

    Applicant: IBM IBM UK

    Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, which comprises based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.

    Abstract translation: 由计算机执行下一条指令访问意图指令。 处理器获得指示访问意图的访问意图指令。 访问意图与下一个顺序指令的操作数相关联。 访问意图表示在下一个顺序指令之后的一个或多个指令的操作数的使用。 计算机执行访问意图指令。 计算机获取下一个顺序指令。 计算机执行下一个顺序指令,其包括基于访问意图,调整下一个顺序指令的操作数的一个或多个缓存行为。

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