公开(公告)号：WO2020068208A1

公开(公告)日：2020-04-02

申请号：PCT/US2019/039068

申请日：2019-06-25

Applicant: INTEL CORPORATION

Inventor： BANDI, Chenchu Punnarao ,  SRIVASTAVA, Amit Kumar ,  ALTMANN, Michael W.

IPC: H04B1/04 ,  H04B17/11

Abstract: An apparatus is provided, where the apparatus includes a transmitter comprising a first stage and a second stage, wherein the first stage is to receive an input voltage and generate bias for the second stage, and wherein the second stage comprises a driver circuitry to transmit data using the bias voltage; and a control circuitry to control generation of the bias, based on receiving a feedback of the input voltage.

公开(公告)号：WO2016167862A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/017227

申请日：2016-02-10

Applicant: INTEL CORPORATION

Inventor： DUDULWAR, Pankaj Vinayak ,  BANDI, Chenchu Punnarao ,  TEH, Lip Khoon ,  TAN, Tat Hin

IPC: G11C7/06 ,  G11C5/14

CPC classification number: H04L7/0037 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1078 ,  G11C11/165 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0812 ,  H04L27/0002

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

Abstract translation: 描述了一种装置，包括：用于感测相对于另一信号的输入信号的输入感测级; 耦合到输入感测级的判定电路，用于确定输入信号是逻辑低还是逻辑高; 以及耦合到输入感测级和决策电路的电源管理电路，其可操作以监视决策电路的状态并根据监视状态禁用输入感测级。 描述了一种装置，其包括：与输入感测级集成的决策电路，其中所述决策电路可操作以在所述时钟信号的相位期间对其内部节点进行预充电; 以及锁存电路，用于锁存所述决策电路的输出。

公开(公告)号：WO2018102034A1

公开(公告)日：2018-06-07

申请号：PCT/US2017/056379

申请日：2017-10-12

Applicant: INTEL CORPORATION

Inventor： BANDI, Chenchu Punnarao ,  SRIVASTAVA, Amit Kumar ,  MOHAPATRA, Sabyasachi

IPC: H04L27/152 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/10 ,  H04L7/0091

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link training logic, and a duty cycle adjustor (DCA). The front-end circuitry is to transmit a training sequence and a forward clock signal to the device and is to receive a strobe signal from the device over a physical transmission media. The DCM is to monitor duty cycle of the strobe signal and duty cycle of the clock signal. The link training logic is to determine a adjustment to the clock signal and is to generate a control signal. The DCA is to receive the clock signal and the control signal and is to adjust the clock signal to generate an adjusted forward clock signal in view of the control signal.

公开(公告)号：WO2017204924A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/027862

申请日：2017-04-17

Applicant: INTEL CORPORATION

Inventor： BANDI, Chenchu Punnarao ,  SRIVASTAVA, Amit Kumar

IPC: H04L7/033 ,  H04L7/00 ,  G06F1/10

CPC classification number: G11C7/222 ,  G06F1/10 ,  H03L7/00 ,  H03L7/091 ,  H04L7/0008 ,  H04L7/005 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/041 ,  H04L25/14

Abstract: In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种装置包括时钟信道，以接收时钟信号并将其分配给多个数据信道。 至少一些数据通道可以包括：第一采样器，用于采样数据; 第二采样器对数据进行采样; 以及去偏移校准电路，用于接收来自第一采样器的第一采样数据和来自第二采样器的第二采样数据，并产生用于对应数据通道中的本地校准信号。 该装置还可以包括全局去偏移校准电路，用于从时钟通道接收时钟信号，从多个数据通道接收第一采样数据和第二采样数据，并且生成用于提供给多个数据的全局校准信号 通道。 描述并要求保护其他实施例。