公开(公告)号：WO2011146823A2

公开(公告)日：2011-11-24

申请号：PCT/US2011/037319

申请日：2011-05-20

Applicant: INTEL CORPORATION ,  WILKERSON, Christopher B. ,  WU, Wei ,  ALAMELDEEN, Alaa R. ,  LU, Shih-Lien ,  CHISHTI, Zeshan A. ,  SOMASEKHAR, Dinesh

Inventor： WILKERSON, Christopher B. ,  WU, Wei ,  ALAMELDEEN, Alaa R. ,  LU, Shih-Lien ,  CHISHTI, Zeshan A. ,  SOMASEKHAR, Dinesh

CPC classification number: G06F11/1064

Abstract: A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.

Abstract translation: 提供了一种使用具有低存储和复杂度开销的多位错误校正码（ECC）的高速缓冲存储器系统。 高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。

公开(公告)号：WO2018004801A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/029175

申请日：2017-04-24

Applicant: INTEL CORPORATION

Inventor： WANG, Zhe ,  WILKERSON, Christopher B. ,  CHISHTI, Zeshan A.

IPC: G06F13/16 ,  G06F12/084

CPC classification number: G06F12/0873 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/124 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/608

Abstract: An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.

Abstract translation: 描述了一种装置，其包括与多级系统存储器接口的存储器控​​制器。 存储器控制器包括最近最少使用（LRU）电路以跟踪保持在多级系统存储器的较高级中的最近最少使用的高速缓存行。 存储器控制器还包括空闲时间预测器电路，以预测多级系统存储器的较低级别的空闲时间。 存储器控制器响应于空闲时间预测器电路系统指示观察到的空闲时间是从多级系统存储器的较高级别向多级别系统存储器的较低级别写入一个或多个较少使用的高速缓存行 预期多级系统存储器的较低级别足够长以容纳从多级系统存储器的较高级别到多级别系统的较低级别的一个或多个较少使用的高速缓存行的写入 存储器中。

公开(公告)号：WO2017027747A1

公开(公告)日：2017-02-16

申请号：PCT/US2016/046628

申请日：2016-08-11

Applicant: INTEL CORPORATION

Inventor： WANG, Ren ,  SCHUMM, Ken ,  CHISHTI, Zeshan A. ,  WILKERSON, Christopher B.

IPC: G06F17/30

CPC classification number: G06F3/0608 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0643 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

Abstract: Examples may include techniques for adaptive compression for data stored in a memory device. The techniques include monitoring a data access pattern to a file or a block for data stored in the memory device and determining a data compression action based on, at least in part, the monitored data access patterns for the file or the block and on an assessed relationship of the file or the block with other files or other blocks. The data compression action including compressing data accessed via the file or the block, decompressing compressed data accessed via the file or the block or no compression action for data accessed via the file or the block.

Abstract translation: 示例可以包括用于存储在存储器设备中的数据的自适应压缩的技术。 这些技术包括监视对存储在存储设备中的数据的文件或块的数据访问模式，以及至少部分地基于所述文件或块的监视数据访问模式以及所评估的数据访问模式来确定数据压缩动作 文件或块与其他文件或其他块的关系。 数据压缩动作包括通过文件或块访问的压缩数据，解压缩经由文件或块访问的压缩数据，或者不经由文件或块访问的数据的压缩动作。

公开(公告)号：WO2017052784A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/045035

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： WANG, Zhe ,  WILKERSON, Christopher B. ,  CHISHTI, Zeshan A. ,  PUGSLEY, Seth H. ,  ALAMELDEEN, Alaa R. ,  LU, Shih-Lien L.

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/6024

Abstract: A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.

Abstract translation: 描述了一种方法，其包括响应于用于第一存储器访问请求的主机侧缓存处的高速缓存未命中，为系统存储器的区域创建第一数据模式访问记录。 第一个存储器访问请求指定系统内存区域内的一个地址。 该方法包括响应于高速缓存未命中从系统存储器获取先前存在的该区域的数据访问模式记录。 先前存在的数据访问模式记录识别区域内先前访问过的数据块。 该方法包括从系统存储器中预取块并将块存储在高速缓存中。

公开(公告)号：WO2016106128A1

公开(公告)日：2016-06-30

申请号：PCT/US2015/066712

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： WANG, Ren ,  HERDRICH, Andrew J. ,  LIU, Yen-Cheng ,  HUM, Herbert H. ,  PARK, Jong Soo ,  HUGHES, Christopher J. ,  VENKATESAN, Namakkal N. ,  MOGA, Adrian C. ,  JALEEL, Aamer ,  CHISHTI, Zeshan A. ,  ERGIN, Mesut A. ,  TSAI, Jr-Shian ,  MIN, Alexander W. ,  TAI, Tsung-Yuan C. ,  MACIOCCO, Christian ,  SANKARAN, Rajesh

IPC: G06F15/173 ,  G06F9/455

CPC classification number: G06F12/0842 ,  G06F9/45558 ,  G06F12/0813 ,  G06F12/0833 ,  G06F12/0893 ,  G06F12/109 ,  G06F2009/45595 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Abstract translation: 实现硬件/软件协同优化的方法和设备，以提高NFV和其他生产者 - 消费者工作负载的VM间通信的性能和能量。 该装置包括具有多级缓存层次结构的多核处理器，包括每个核心的L1和L2缓存以及共享的最后一级缓存（LLC）。 提供了一个或多个机器级指令，用于主动地将高速缓存行从低级缓存级别降级到更高的高速缓存级别，包括将高速缓存行从L1 / L2高速缓存降级到LLC。 还提供了用于在多插槽NUMA架构系统中实现硬件/软件协同优化的技术，其中高速缓存线可以被选择性地降级并被推送到远程插座中的LLC。 此外，技术是在多插槽系统中实现早期窥探的技术，以减少在远程插槽上访问高速缓存线时的延迟。

公开(公告)号：WO2014092801A1

公开(公告)日：2014-06-19

申请号：PCT/US2013/048486

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： WANG, Ren ,  AHMAD, Samih A. ,  DELANO, Eric ,  SHAH, Pinkesh J. ,  CHISHTI, Zeshan A. ,  MACIOCCO, Christian ,  TAI, Tsung-Yuan C.

IPC: G06F1/32 ,  G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0802 ,  G06F1/32 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0811 ,  G06F2212/1028 ,  Y02D10/13

Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。 该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。 耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。 描述和要求保护其他实施例。