公开(公告)号：WO2018001528A1

公开(公告)日：2018-01-04

申请号：PCT/EP2016/065598

申请日：2016-07-01

Applicant: INTEL CORPORATION ,  GONZALEZ, Alejandro Duran ,  BLANKENSHIP, Robert G.

Inventor： GONZALEZ, Alejandro Duran ,  BLANKENSHIP, Robert G. ,  BERNAT, Francesc Guim ,  KUMAR, Karthik ,  DIMITROV, Martin P. ,  WILLHALM, Thomas

IPC: G06F12/08 ,  G06F12/122 ,  G06F12/127 ,  G06F12/128 ,  G06F12/0811

CPC classification number: G06F12/128 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/127 ,  G06F2212/1016

Abstract: A processor includes a processing core and a caching circuit, communicatively coupled to the processing core, comprising a dead block predictor (DBP) to predict that a cache line in a last-level cache (LLC) is not to be accessed until an eviction from the LLC, wherein responsive to predicting that the cache line is not to be accessed until the eviction, the caching circuit is to issue an evict message to a memory controller, the evict message comprising a flag indicating a DBP status of the cache line.

Abstract translation: 处理器包括通信地耦合到处理核心的处理核心和高速缓存电路，其包括用于预测最后级别高速缓存（LLC）中的高速缓存行是死区块预测器（DBP）的死区块预测器 在从所述LLC驱逐之前不被访问，其中响应于预测所述高速缓存行将不被访问直到所述驱逐，所述高速缓存电路将向驱动器发出驱逐消息，所述驱逐消息包括指示 缓存行的DBP状态。

公开(公告)号：WO2018059656A1

公开(公告)日：2018-04-05

申请号：PCT/EP2016/001631

申请日：2016-09-30

Applicant: INTEL CORPORATION ,  LU, Patrick ,  KUMAR, Karthik ,  WILLHALM, Thomas ,  GUIM BERNAT, Francesc ,  DIMITROV, Martin P.

Inventor： LU, Patrick ,  KUMAR, Karthik ,  WILLHALM, Thomas ,  GUIM BERNAT, Francesc ,  DIMITROV, Martin P.

IPC: G06F12/0862 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811

Abstract: An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

Abstract translation: 描述了一种装置。 该设备包括主存储器控制逻辑电路，其包括预取智能逻辑电路。 预取智能电路根据加载指令的读取结果来确定依赖于读取结果的依赖性加载的地址，并且将对依赖性加载的读取请求引导至主存储器以提取依赖性加载的数据。 / p>

公开(公告)号：WO2017171798A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025299

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： GUIM BERNAT, Francesc ,  WILLHALM, Thomas ,  KUMAR, Karthik ,  DIMITROV, Martin P. ,  RAMANUJAN, Raj K.

IPC: G06F3/06

Abstract: Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与用于将许多存储操作原子写入远程节点的结构弹性支持有关的方法和设备。 在一个实施例中，非易失性存储器存储对应于多个写入操作的数据。 第一节点包括执行一个或多个操作（响应于多个写操作）以使得数据在第二节点处原子地存储的逻辑。 多个写入操作被原子地绑定到事务，并且响应于事务的释放，数据被写入到非易失性存储器。 其他实施例也被公开和要求保护。

公开(公告)号：WO2017074612A1

公开(公告)日：2017-05-04

申请号：PCT/US2016/053060

申请日：2016-09-22

Applicant: INTEL CORPORATION

Inventor： KUMAR, Karthik ,  DIMITROV, Martin P.

IPC: G06F9/30 ,  G06F12/0862

CPC classification number: G06F9/30047 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/20 ,  G06F2212/452

Abstract: In one embodiment, a processor includes a core having a fetch logic to fetch instructions, a decode logic to decode a first persistent memory prefetch instruction and provide the decoded first persistent memory prefetch instruction to a control logic. In turn, the control logic is to enable prefetch of data requested by the first persistent memory prefetch instruction and storage of the data in a location external to the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有用于提取指令的提取逻辑的核心，用于解码第一持久存储器预取指令并将经解码的第一持久存储器预取指令提供给控制逻辑的解码逻辑。 进而，控制逻辑能够预取第一持久性存储器预取指令所请求的数据并将数据存储在处理器外部的位置中。 描述并要求保护其他实施例。