公开(公告)号：WO2019133172A1

公开(公告)日：2019-07-04

申请号：PCT/US2018/063054

申请日：2018-11-29

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  GENDLER, Alexander ,  ROTEM, Efraim ,  COHEN, Moshe ,  MALLICK, Asit K. ,  BRANDT, Jason, W. ,  SUBRAMANIAM, Kameswar ,  FELLMAN, Nathan ,  SHAFI, Hisham

IPC: G06F13/36

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

公开(公告)号：WO2012040708A2

公开(公告)日：2012-03-29

申请号：PCT/US2011/053266

申请日：2011-09-26

Applicant: INTEL CORPORATION ,  PHILLIPS, James E. ,  SUBRAMANIAM, Kameswar

Inventor： PHILLIPS, James E. ,  SUBRAMANIAM, Kameswar

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/305 ,  G06F9/06

CPC classification number: G06F9/30087 ,  G06F9/3842 ,  G06F9/3857

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract translation: 包括执行逻辑的装置，所述执行逻辑包括执行指令的电路以及与执行逻辑耦合的指令执行调度器逻辑。 指令执行调度器逻辑将在提交状态更新指令处接收执行。 指令执行调度器逻辑在提交状态更新逻辑处包括将等待调度执行状态更新指令处的执行以用于执行直到提交状态更新指令处的执行是下一个提交指令为止。 其他装置，方法和系统也被公开。

公开(公告)号：WO2019190685A1

公开(公告)日：2019-10-03

申请号：PCT/US2019/019961

申请日：2019-02-28

Applicant: INTEL CORPORATION

Inventor： SHANBHOGUE, Vedvyas ,  ANANTHAKRISHNAN, Avinash N. ,  GORBATOV, Eugene ,  FENGER, Russell ,  RAJ, Ashok ,  SUBRAMANIAM, Kameswar

IPC: G06F9/445 ,  G06F11/30 ,  G06F11/34

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

公开(公告)号：WO2023027823A1

公开(公告)日：2023-03-02

申请号：PCT/US2022/037037

申请日：2022-07-14

Applicant: INTEL CORPORATION

Inventor： SUBRAMANIAM, Kameswar ,  RUSSELL, Christopher

IPC: G06F12/1027 ,  G06F13/16 ,  G06F3/06

Abstract: Methods and apparatus relating to issue, execution, and backend driven frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input, and generates one or more outputs based at least in part on the static input and the dynamic input. The DTL circuitry generates the one or more outputs prior to commencement of speculation operations in a processor. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2012040531A3

公开(公告)日：2012-03-29

申请号：PCT/US2011/052875

申请日：2011-09-23

Applicant: INTEL CORPORATION ,  COMBS, Jonathan D. ,  SUBRAMANIAM, Kameswar ,  BRANDT, Jason

Inventor： COMBS, Jonathan D. ,  SUBRAMANIAM, Kameswar ,  BRANDT, Jason

IPC: G06F9/30 ,  G06F9/305 ,  G06F9/06

Abstract: An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.