公开(公告)号：WO2012108919A2

公开(公告)日：2012-08-16

申请号：PCT/US2011/061283

申请日：2011-11-17

Applicant: INTEL CORPORATION ,  BENNETT, Joseph, A. ,  LI, Guoging ,  SOMAYAZULU, Vallabhajosyula, S. ,  HAYEK, George, R. ,  PRAT, Gideon ,  KAMBHATLA, Srikanth

Inventor： BENNETT, Joseph, A. ,  SOMAYAZULU, Vallabhajosyula, S. ,  HAYEK, George, R. ,  PRAT, Gideon ,  KAMBHATLA, Srikanth

IPC: H04L12/56 ,  H04N7/24 ,  H04L29/06

CPC classification number: H04L69/22 ,  H04N21/2381 ,  H04N21/4381 ,  H04N21/643

Abstract: A data packet or payload defined by a first format, is generated and is wrapped with headers as defined by a second format, and is processed through a pass through mechanism for transmission based on the second format. The processing includes adding or encapsulating the payload in the transmission data packet. When receiving the transmitted data packet, the theaders may be parsed, and the payload processed.

Abstract translation: 产生由第一格式定义的数据分组或有效负载，并且由第二格式定义的报头包裹，并且通过基于第二格式传输的传递机制进行处理。 该处理包括将有效载荷添加或封装在传输数据包中。 当接收到发送的数据包时，可以解析器，并且处理有效载荷。

公开(公告)号：WO2013095417A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066404

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  LI, Guoqing ,  BENNETT, Joseph, A. ,  PRAT, Gideon ,  TRAININ, Solomon, B. ,  LEE, Sang-Hee ,  SOMAYAZULU, Vallabhajosyula, Z. ,  HAYEK, George, R. ,  BROUILLETTE, Pat ,  LOUKIANOV, Dmitrii, A.

Inventor： LI, Guoqing ,  BENNETT, Joseph, A. ,  PRAT, Gideon ,  TRAININ, Solomon, B. ,  LEE, Sang-Hee ,  SOMAYAZULU, Vallabhajosyula, Z. ,  HAYEK, George, R. ,  BROUILLETTE, Pat ,  LOUKIANOV, Dmitrii, A.

IPC: H04L12/56 ,  H04N21/242

CPC classification number: H04N21/242 ,  H04N21/23608 ,  H04N21/4305 ,  H04N21/6131

Abstract: An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR)value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

Abstract translation: 提供了一种用于确定程序时钟参考（PCR）值有效性的方法，用于避免不准确的可变延迟引用（VDR）值，并且用于避免无线显示扩展的序列号和分组号之间的数据分组的不匹配。 该方法包括确定生成具有可选PCR值，VDR值和有效性指示符的数据分组载体。 该方法还可以涉及处理数据分组载波以确定数据分组载波是否具有任选的PCR值。 该方法还可以包括至少部分地导致至少部分地基于来自数据分组载体的确定的不存在可选PCR值来生成替代PCR值。

公开(公告)号：WO1998029811A1

公开(公告)日：1998-07-09

申请号：PCT/US1997021904

申请日：1997-11-24

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HAYEK, George, R. ,  VENKATARAMAN, Radhakrishnan ,  AJANOVIC, Jasmin

IPC: G06F11/08

CPC classification number: G06F11/106 ,  G06F11/1028 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0409

Abstract: Error correction circuitry (101) attempts to detect and correct, on-the-fly, erroneous words from RAM (102) within a computer system. Correctable errors are scrubbed without delaying the memory access cycle. The address of the section or row of RAM containing the correctable error is latched (130) for later use by a firmware-implemented interrupt-driven scrub routine (104) that reads and rewrites each word within the indicated memory section, resulting in the erroneous word being corrected on-the-fly and rewritten correctly. If the memory section size exceeds a threshold, the scrub process is divided into smaller subprocesses that are distributed in time using a delayed interrupt mechanism. Subprocess duration is kept short enough to avoid impairing the computer system response time. System management interrupts (120) and firmware (104) make the scrub routine independent of and transparent to the operating systems that may be run on the computer system.

Abstract translation: 错误校正电路（101）尝试从计算机系统内的RAM（102）中检测并纠正错误的单词。 擦除可纠正的错误，而不会延迟内存访问周期。 锁存包含可纠正错误的RAM的部分或一行的地址（130），供以后使用的固件实现的中断驱动擦除程序（104）读取并重写所指示的存储器部分中的每个字，导致错误 字被正确地修正并被正确地重写。 如果存储器部分大小超过阈值，则擦除处理被划分为使用延迟中断机制在时间上分布的更小的子处理。 子过程持续时间保持足够短以避免损害计算机系统响应时间。 系统管理中断（120）和固件（104）使擦洗程序独立于可能在计算机系统上运行的操作系统并且是透明的。

公开(公告)号：WO1996021226A1

公开(公告)日：1996-07-11

申请号：PCT/US1995016880

申请日：1995-12-28

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HAYEK, George, R. ,  NARDONE, Joe, M. ,  KUNDU, Aniruddha ,  BAINS, Kuljit, S.

IPC: G11C07/00

CPC classification number: G11C7/1018 ,  G11C7/1024

Abstract: A memory controller (105) having a data strobe (250) that tracks the column address strobe signal in a computer system having Extended Data Out (EDO) DRAMs (230). The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column address strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to the data strobe signal, at approximately the center of the valid window.

Abstract translation: 具有在具有扩展数据输出（EDO）DRAM（230）的计算机系统中跟踪列地址选通信号的数据选通（250）的存储器控​​制器（105）。 数据选通信号以预定的延迟跟随列存取选通信号，因此列地址选通信号中的任何偏移固有地包括在数据选通信号内。 结果，可以在有效窗口的大约中心处响应于数据选通信号来锁存数据。