公开(公告)号：WO2017171869A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025709

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： MAERTZ, Brian ,  WIEGAND, Christopher, J. ,  OEULLETTE, Daniel, G. ,  RAHMAN, MD Tofizur ,  GOLONZKA, Oleg ,  BROCKMAN, Justin, S. ,  GHANI, Tahir ,  DOYLE, Brian, S. ,  O'BRIEN, Kevin, P. ,  DOCZY, Mark, L. ,  OGUZ, Kaan

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

Abstract translation: 一种装置，包括：布置在由字线和位线限定的栅格中的存储器单元阵列，存储器单元包括电阻存储器组件和存取晶体管， 其中所述存取晶体管包括相对于相关字线以锐角设置的扩散区。 一种方法包括蚀刻基板以形成多个鳍片，每个鳍片包括具有长度尺寸的主体，所述主体包括多个第一结区域和多个第二结区域，所述多个第一结区域和多个第二结区域彼此大致平行并且被成角度的沟道区域 从第二结区的起始处开始第一结区的末端; 去除间隔物材料; 并在多个鳍片中的每个鳍​​片的沟道区域上引入栅电极。