公开(公告)号：WO2019005160A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040500

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  OUELLETTE, Daniel G. ,  WU, Stephen Y. ,  BROCKMAN, Justin S. ,  WIEGAND, Christopher J. ,  GOLONZKA, Oleg ,  RAHMAN, Tofizur ,  SMITH, Angeline K. ,  DOYLE, Brian S. ,  ALZATE VINASCO, Juan G. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L.

Inventor： OUELLETTE, Daniel G. ,  WU, Stephen Y. ,  BROCKMAN, Justin S. ,  WIEGAND, Christopher J. ,  GOLONZKA, Oleg ,  RAHMAN, Tofizur ,  SMITH, Angeline K. ,  DOYLE, Brian S. ,  ALZATE VINASCO, Juan G. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L.

IPC: H01L43/10 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device includes a bottom electrode comprising a non-stoichiometric tantalum nitride layer. A synthetic antiferromagnetic layer is disposed above the bottom electrode. A fixed magnet is disposed above the synthetic antiferromagnetic layer. A tunnel barrier is disposed above the fixed magnet. A free magnet is above the tunnel barrier and a top electrode is disposed above the free magnet.

公开(公告)号：WO2019005082A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040136

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： KUO, Charles C. ,  ATANASOV, Sarah ,  DOCZY, Mark L. ,  OGUZ, Kaan ,  SURI, Satyarth

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: MTJ material stacks including one or more material layers that have outdiffused one or more dopants through a layer sidewall edge, MTJ devices employing such stacks, and computing platforms employing such MTJ devices. A free magnet layer or fixed magnet layer may include a dopant, such as boron. A liner layer may be deposited over an MTJ stack, for example in close proximity to the edge of at least one of the fixed or free magnet layers. During a thermal anneal, a dopant, such as boron, may be gettered by the liner. Dopant gettering by the liner may facilitate changes with in the MTJ stack, such as development of perpendicular magnetic anisotropy within a magnet layer. Following dopant gettering, the liner may be retained, or at least partially removed as sacrificial.

公开(公告)号：WO2019005076A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040044

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： KUO, Charles ,  CHAUDHRY, Anurag ,  OGUZ, Kaan

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: MTJ material stacks including a carbon-doped ferromagnetic material, MTJ devices employing such stacks, and computing platforms employing such MTJ devices. A free magnet with one or more ferromagnetic material layer that includes carbon may display improved stability and low damping. A fixed magnet with one or more ferromagnetic material layer may also include carbon.

公开(公告)号：WO2018236361A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/038387

申请日：2017-06-20

Applicant: INTEL CORPORATION ,  MAJHI, Prashant ,  DOYLE, Brian S. ,  O'BRIEN, Kevin P. ,  SHARMA, Abhishek A. ,  KARPOV, Elijah V. ,  OGUZ, Kaan

Inventor： MAJHI, Prashant ,  DOYLE, Brian S. ,  O'BRIEN, Kevin P. ,  SHARMA, Abhishek A. ,  KARPOV, Elijah V. ,  OGUZ, Kaan

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

Abstract: Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

公开(公告)号：WO2018125204A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069473

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： RAHMAN, MD Tofizur ,  WIEGAND, Christopher J. ,  OGUZ, Kaan ,  BROCKMAN, Justin S. ,  OUELLETTE, Daniel G. ,  MAERTZ, Brian ,  O'BRIEN, Kevin P. ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  GOLONZKA, Oleg ,  GHANI, Tahir

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.

公开(公告)号：WO2018125085A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/068904

申请日：2016-12-28

Applicant: INTEL CORPORATION ,  BROCKMAN, Justin ,  WIEGAND, Christopher ,  RAHMAN, MD Tofizur ,  OUELETTE, Daniel ,  SMITH, Angeline ,  ALZATE VINASCO, Juan ,  KUO, Charles ,  DOCZY, Mark ,  OGUZ, Kaan ,  O'BRIEN, Kevin ,  DOYLE, Brian ,  GOLONZKA, Oleg ,  GHANI, Tahir

Inventor： BROCKMAN, Justin ,  WIEGAND, Christopher ,  RAHMAN, MD Tofizur ,  OUELETTE, Daniel ,  SMITH, Angeline ,  ALZATE VINASCO, Juan ,  KUO, Charles ,  DOCZY, Mark ,  OGUZ, Kaan ,  O'BRIEN, Kevin ,  DOYLE, Brian ,  GOLONZKA, Oleg

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.

公开(公告)号：WO2018004698A1

公开(公告)日：2018-01-04

申请号：PCT/US2016/040875

申请日：2016-07-01

Applicant: INTEL CORPORATION ,  RAHMAN, MD Tofizur ,  WIEGAND, Christopher J. ,  MAERTZ, Brian ,  OUELLETTE, Daniel G. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  DOCZY, Mark L. ,  BERGSTROM, Daniel B. ,  BROCKMAN, Justin S. ,  GOLONZKA, Oleg ,  GHANI, Tahir

Inventor： RAHMAN, MD Tofizur ,  WIEGAND, Christopher J. ,  MAERTZ, Brian ,  OUELLETTE, Daniel G. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  DOCZY, Mark L. ,  BERGSTROM, Daniel B. ,  BROCKMAN, Justin S. ,  GOLONZKA, Oleg ,  GHANI, Tahir

IPC: H01L43/02 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

Abstract translation: 材料层堆叠结构提供具有改善的垂直磁各向异性（PMA）特性的磁性隧道结（MTJ）。 在一个实施例中，材料层堆叠的自由磁层设置在隧道势垒层和氧化镁（Mg）的盖层之间。 自由磁层包括基本上由钴原子，铁原子和硼原子的组合构成的钴 - 铁 - 硼（CoFeB）体。 在与自由磁性层与隧道势垒层的界面邻接的第一区域中，CoFeB主体的第一硼质量分数等于或大于25％（例如，等于或大于27％）。 在另一个实施例中，第一硼质量分数大于CoFeB主体的第二区域中的第二硼质量分数，所述第二区域邻接自由磁层与帽层的界面。

公开(公告)号：WO2018004652A1

公开(公告)日：2018-01-04

申请号：PCT/US2016/040686

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： KUO, Charles C. ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  O'BRIEN, Kevin P.

IPC: H01L29/73 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/0688 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/11514 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/228 ,  H01L29/41733

Abstract: Techniques are disclosed for forming an integrated circuit (IC) including a front-end tunnel junction device plus a back-end transistor or transistor-based device. For ease of reference, the combination of the two devices may be referred to herein as a "1T-1TJ" configuration, where the "1T" portion represents the back-end transistor or transistor-based device and the "1TJ" portion represents the front-end tunnel junction device. As will be apparent in light of this disclosure, in some embodiments, 1T-1TJ configuration can be used for memory applications, where the front-end tunnel junction device can be used as the switching element to store data (e.g., a '1' or '0') and the back-end transistor or transistor-based device can be used to write and/or read the tunnel junction switching element. Benefits can be derived from forming the tunnel junction device during front-end IC processing. Other embodiments may be described and/or disclosed.

Abstract translation: 公开了用于形成包括前端隧道结器件加上后端晶体管或基于晶体管的器件的集成电路（IC）的技术。 为了便于参考，这两个装置的组合可以在本文中被称为“1T-1TJ” 配置，其中“1T” 部分表示后端晶体管或基于晶体管的器件，而“1TJ” 部分代表前端隧道连接装置。 根据本公开内容将显而易见的是，在一些实施例中，1T-1TJ配置可以用于存储器应用，其中前端隧道结器件可以用作开关元件以存储数据（例如'1' 或'0'），并且后端晶体管或基于晶体管的器件可以用于写入和/或读取隧道结切换元件。 在前端IC处理期间形成隧道结器件可以带来好处。 其他实施例可以被描述和/或公开。

公开(公告)号：WO2017171848A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025624

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  WIEGAND, Christopher J ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  RAHMAN, MD Tofizur ,  GOLONZKA, Oleg ,  GHANI, Tahir

IPC: H01L21/66 ,  H01L43/12 ,  G01R23/16 ,  G01R31/26

CPC classification number: G01R31/2831 ,  G01N24/10 ,  G01R31/315 ,  G01R33/098 ,  G01R33/60 ,  G01R35/00 ,  H01L22/14 ,  H01L43/12

Abstract: Techniques are disclosed for carrying out ferromagnetic resonance (FMR) testing on whole wafers populated with one or more buried magnetic layers. The techniques can be used to verify or troubleshoot processes for forming the buried magnetic layers, without requiring the wafer to be broken. The techniques can also be used to distinguish one magnetic layer from others in the same stack, based on a unique frequency response of that layer. One example methodology includes moving a wafer proximate to a waveguide (within 500 microns, but without shorting), energizing a DC magnetic field near the target measurement point, applying an RF input signal through the waveguide, collecting resonance spectra of the frequency response of the waveguide, and decomposing the resonance spectra into magnetic properties of the target layer. One or both of the DC magnetic field and RF input signal can be swept to generate a robust set of resonance spectra.

Abstract translation: 公开了用于在填充有一个或多个掩埋磁性层的整个晶片上执行铁磁共振（FMR）测试的技术。 这些技术可用于验证或排除形成掩埋磁性层的过程，而不需要破碎晶片。 基于该层的唯一频率响应，该技术还可用于将同一叠层中的一个磁层与其他磁层区分开来。 一个示例性方法包括移动靠近波导（在500微米内，但没有短路）的晶片，激励目标测量点附近的DC磁场，通过波导施加RF输入信号，收集波导的频率响应的谐振频谱 波导，并将谐振频谱分解成目标层的磁性。 直流磁场和射频输入信号中的一个或两个可以被扫描以产生一组强大的共振谱。

公开(公告)号：WO2017171837A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025576

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： O'BRIEN, Kevin P. ,  DOYLE, Brian S. ,  OGUZ, Kaan ,  KUO, Charles C. ,  DOCZY, Mark L. ,  INDUKURI, Tejaswi K.

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L27/1159 ,  G11C11/221 ,  G11C11/223 ,  H01L27/11507 ,  H01L27/11587 ,  H01L29/78391

Abstract: A monocrystalline metal-oxide stack including a ferroelectric (FE) tunneling layer and a buffer layer is epitaxially grown on a growth substrate. A first poly crystalline metal electrode layer is deposited over the tunneling layer. A bonding material layer is further deposited over the electrode layer. The bonding material layer is then bonded to a material layer on a front or back side of a host substrate that further comprises a transistor cell. Once bonded, the growth substrate may be removed from the metal-oxide stack to complete a transfer of the metal-oxide stack from the growth substrate to the host substrate. A second poly crystalline metal electrode layer is then deposited over the exposed buffer layer, placing both electrodes in close proximity to the FE tunneling layer.

Abstract translation: 包括铁电（FE）隧穿层和缓冲层的单晶金属氧化物堆叠体在生长衬底上外延生长。 在隧穿层上沉积第一多晶金属电极层。 进一步在电极层上沉积结合材料层。 然后将接合材料层接合到还包括晶体管单元的主基板的正面或背面上的材料层。 一旦结合，可将生长衬底从金属氧化物堆叠移除以完成金属氧化物堆叠从生长衬底到主衬底的转移。 然后在暴露的缓冲层上沉积第二多晶金属电极层，使两个电极紧靠FE隧穿层。