公开(公告)号：WO2021061144A1

公开(公告)日：2021-04-01

申请号：PCT/US2019/053339

申请日：2019-09-27

Applicant: INTEL CORPORATION

Inventor： DE ANDRADE TABARANI SANTOS, Filipe ,  ROITHMEIER, Andreas ,  GOSSMANN, Timo ,  AAMIR, Syed, Ahmed ,  ZINKE, Rinaldo

IPC: H03M1/66 ,  H03M1/00

Abstract: A RFDAC comprising an array of unit-cell power amplifiers, wherein the array comprises a first plurality of unit-cell power amplifiers, a second plurality of unit-cell power amplifiers, and a third plurality of unit-cell power amplifiers; wherein the first plurality of unit-cell power amplifiers are configured to operate in accordance with a first clock; wherein the second plurality of unit-cell power amplifiers are configured to operate in accordance with a second clock; wherein the third plurality of unit-cell power amplifiers are configured to operate in accordance with the first clock or the second clock. The RFDAC also comprising a decoder configured to output the first clock and an enablement signal of the first clock for the first plurality; output the second clock and an enablement signal of the second clock for the second plurality; distinguish between the first clock and the second clock for the third plurality.

公开(公告)号：WO2018052630A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/047134

申请日：2017-08-16

Applicant: INTEL CORPORATION

Inventor： BROUSSEV, Svetozar ,  LEISTNER, Andreas Jörn ,  ROITHMEIER, Andreas ,  GUSTEDT, Thomas

IPC: H03K17/687 ,  H03K17/693 ,  H04B1/44

Abstract: Various designs for MOS transistor-based RF switch topologies for high speed capacitive tuning of oscillators switch circuits include a main switch device comprising a gate connected to a control terminal, a drain connected to a first terminal that is connected to the first capacitor, and a source connected to a second terminal that is connected to the second capacitor. The switch further comprises a first NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the first terminal. The switch further comprises a second NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the second terminal. The switch further comprises a pair of PMOS devices each having drains connected respectively to the first and second terminals.

Abstract translation: 用于高速电容调谐振荡器开关电路的基于MOS晶体管的RF开关拓扑的各种设计包括主开关装置，其包括连接到控制端子的栅极，连接到第一端子的漏极， 连接到第一电容器，源极连接到连接到第二电容器的第二端子。 该开关还包括第一NMOS器件，该第一NMOS器件具有连接到主开关器件栅极的栅极，连接到地的源极以及连接到第一端子的漏极。 该开关还包括第二NMOS器件，该第二NMOS器件具有连接到主开关器件栅极的栅极，连接到地的源极以及连接到第二端子的漏极。 该开关还包括一对PMOS器件，每个器件的漏极分别连接到第一和第二端子。

公开(公告)号：WO2019190567A1

公开(公告)日：2019-10-03

申请号：PCT/US2018/025598

申请日：2018-03-31

Applicant: INTEL CORPORATION

Inventor： WICPALEK, Christian ,  ROITHMEIER, Andreas ,  LEISTNER, Andreas ,  GUSTEDT, Thomas ,  DIETL-STEINMAURER, Herwig ,  BUCKEL, Tobias

IPC: H03L7/08 ,  H03L7/085 ,  H03L7/099

Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.