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公开(公告)号：WO2022231818A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/023889
申请日：2022-04-07
Applicant: QUALCOMM INCORPORATED
Inventor： SAPUTRA, Nitz , SWAMINATHAN, Ashok , WEIL, Andrew
Abstract: Certain aspects of the present disclosure provide a digital-to-analog conversion circuit. The digital-to-analog conversion circuit generally includes a detection circuit configured to detect digital transitions in a digital input signal. The digital-to-analog conversion circuit also includes a clock-gating circuit having an input coupled to an output of the detection circuit. The clock-gating circuit is configured to gate a clock signal for the digital-to-analog conversion circuit based on an output signal from the detection circuit.
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公开(公告)号：WO2022139791A1
公开(公告)日：2022-06-30
申请号：PCT/US2020/066407
申请日：2020-12-21
Applicant: GOOGLE LLC
Abstract: This disclosure describes apparatuses, methods, and techniques that enable a computing device to support a dynamic range of audio quality, varying bandwidths, varying sampling rates, numerous effective number of bits (ENOBs) resolutions, conserve power during an overall usage of the computing device, and enhance a user experience. To do so, the computing device utilizes a reconfigurable analog-to-digital converter (ADC). The reconfigurable ADC includes a successive-approximation-register (SAR) ADC, a noise-canceling circuit, and a noise-shaping circuit. The reconfigurable ADC can selectively operate in different modes of operation, in part, by enabling or disabling the noise-canceling circuit and the noise-shaping circuit.
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3.发明申请
公开(公告)号：WO2021258090A1
公开(公告)日：2021-12-23
申请号：PCT/US2021/070308
申请日：2021-03-25
Applicant: MICROCHIP TECHNOLOGY INCORPORATED
Inventor： SUNDERDIEK, Gregor Hubert
Abstract: Analog signal measurement and related circuitry, systems, and methods are disclosed. Circuitry includes timing circuitry configured to assert a first enable signal at a first time and a second enable signal at a second time. The circuitry also includes an operational amplifier circuit configured to enable responsive to the assertion of the first enable signal. The operational amplifier circuit is configured to receive an analog input signal and, if enabled, generate an amplified analog input signal responsive to the analog input signal. The circuitry further includes signal analyzing circuitry configured to enable responsive to the assertion of the first enable signal, compare the amplified analog input signal to one or more threshold values responsive to the assertion of the second enable signal, and generate an alert signal responsive to a determination that the amplified analog input signal falls outside of the one or more threshold values.
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公开(公告)号：WO2021115760A1
公开(公告)日：2021-06-17
申请号：PCT/EP2020/082901
申请日：2020-11-20
Applicant: ENDRESS+HAUSER SE+CO. KG
Inventor： FRÜHAUF, Dietmar , BRAUN, Marco , FRANKE, Alexander
Abstract: Die Erfindung betrifft ein Verfahren zur Optimierung einer Mess-Rate eines ersten Feldgerätes (11) in einem Mess-System (1). Zur Anwendung des Verfahrens muss das Mess-System (1) neben dem ersten Feldgerät (11) zumindest ein zweites Feldgerät (12) umfassen, bei dem zumindest die Messgröße (L) des ersten Feldgerätes (11) mit der Messgröße (f) des zweiten Feldgerätes (12) korreliert. Das Verfahren beruht darauf, ein jeweils spezifisches Korrelations-Muster zwischen der ersten Messgröße (L) und der zweiten Messgröße (f) anhand von in einer Einlernphase gemessenen Messwerten zu bestimmen. Hierdurch ist es erfindungsgemäß möglich, während des regulären Messbetriebs zumindest die Messwerte des zweiten Feldgerätes (12) auf das Korrelations-Muster hin zu prüfen und die Mess-Rate des ersten Feldgerätes (11) während des entsprechenden Zeitfensters (Δt) zu ändern. Hierdurch kann insbesondere bei Batteriebetriebenen Feldgeräten (11, 12, 13) die Einsatzdauer bzw. die Verfügbarkeit in der Prozessanlage erhöht werden, so dass Stillstandszeiten der Prozessanlage vermieden werden können.
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公开(公告)号：WO2021061547A1
公开(公告)日：2021-04-01
申请号：PCT/US2020/051742
申请日：2020-09-21
Inventor： NARULA, Rohit , TADEPARTHY, Preetam Charan Anand , JAIN, Mayank
IPC: H03M1/00
Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC, 408) having a resistor network. The resistor network includes a first and second segments (B0-B9, T1-T15). The first segment (B0-B9, T1-T15) includes a first switch (SW) coupled between a first supply voltage node and a first set of resistors (R). The second segment (T13, T14) includes a second switch (SW) coupled between the first supply voltage node and a second set (450) of resistors. The first segment includes a third switch coupled in series with a second resistor. The series-combination of the third switch and second resistor are coupled in parallel with at least one resistor of the first set of resistors. The second segment includes a fourth switch coupled in series with a third resistor. The series-combination of the fourth switch and third resistor is coupled in parallel with at least one resistor of the second set of resistors.
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Patent Agency Ranking6.发明申请
公开(公告)号：WO2021061144A1
公开(公告)日：2021-04-01
申请号：PCT/US2019/053339
申请日：2019-09-27
Applicant: INTEL CORPORATION
Inventor： DE ANDRADE TABARANI SANTOS, Filipe , ROITHMEIER, Andreas , GOSSMANN, Timo , AAMIR, Syed, Ahmed , ZINKE, Rinaldo
Abstract: A RFDAC comprising an array of unit-cell power amplifiers, wherein the array comprises a first plurality of unit-cell power amplifiers, a second plurality of unit-cell power amplifiers, and a third plurality of unit-cell power amplifiers; wherein the first plurality of unit-cell power amplifiers are configured to operate in accordance with a first clock; wherein the second plurality of unit-cell power amplifiers are configured to operate in accordance with a second clock; wherein the third plurality of unit-cell power amplifiers are configured to operate in accordance with the first clock or the second clock. The RFDAC also comprising a decoder configured to output the first clock and an enablement signal of the first clock for the first plurality; output the second clock and an enablement signal of the second clock for the second plurality; distinguish between the first clock and the second clock for the third plurality.
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公开(公告)号：WO2021017516A1
公开(公告)日：2021-02-04
申请号：PCT/CN2020/082966
申请日：2020-04-02
Applicant: 华为技术有限公司
IPC: H04B10/50 , H04B10/516 , H01S5/10 , G02F7/00 , H03M1/00
Abstract: 本申请提供信号处理装置和信号处理方法。本申请提供的信号处理装置包括：采样单元、合束器和光学谐振腔。采样单元与合束器相连，合束器与光学谐振腔相连；采样单元用于：使用光脉冲信号对模拟信号进行采样，输出采样光脉冲信号；合束器用于：将采样光脉冲信号与多波长光信号合成第一光信号；光学谐振腔用于：根据第一光信号进行谐振，输出第一光信号中的第二光信号，第二光信号的波长等于光学谐振腔的谐振波长。本申请提供的信号处理装置和信号处理方法，能够根据采样后的光脉冲的强度实现光量化，以便于实现模拟信号至数字信号的转换。
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公开(公告)号：WO2020191368A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/024034
申请日：2020-03-20
Applicant: LUMINOUS COMPUTING, INC.
Inventor： NAHMIAS, Mitchell A. , GAO, Michael
Abstract: A system for analog-to-digital conversion, preferably including one or more optical inputs, optical sources, phase remodulators, and/or photonic circuits, and optionally including detector banks and/or digital electronics. A method for analog-to-digital conversion, preferably including receiving an optical input signal, generating a phase- modulated optical signal, and/or generating a plurality of optical outputs, and optionally including generating a plurality of electrical outputs and/or encoding a digital representation of the outputs.
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公开(公告)号：WO2020172769A1
公开(公告)日：2020-09-03
申请号：PCT/CN2019/076055
申请日：2019-02-25
Applicant: 深圳市汇顶科技股份有限公司
IPC: H03M1/00
Abstract: 本申请公开了一种数据转换器(112)。所述数据转换器包括输入端(98)、数模转换器(116)以及映射单元(114)。所述输入端用来接收输入信号。所述数模转换器包括多个数模转换器单元用来产生输出信号。所述映射单元，耦接于所述输入端以及所述数模转换器之间，用来使所述多个数模转换器单元依据所述多个数模转换器单元的特定电气特性来在所述多个数模转换器单元被选通的一相对顺序上等效地排列以进行数字模拟转换。本申请另提供模数转换器、数模转换器及相关芯片。
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公开(公告)号：WO2020033022A1
公开(公告)日：2020-02-13
申请号：PCT/US2019/030848
申请日：2019-05-06
Applicant: RAYTHEON COMPANY
Inventor： IVES, Philip H. , ANAGNOST, John J.
Abstract: A position sensor device includes a sensor head with a sensor coil, and an analog-to-digital (A/D) converter for digitizing output from the sensor coil, and sending the digital input to electronics of the device for further processing. The A/D converter is located closer to the coil than it is to the electronics, which may be in an electronics box mounted remotely from the sensor head. The A/D converter may be a part of the sensor head, may be adjacent to the sensor head, and/or may be connected to the sensor coil by an analog output cable. The analog output cable between the sensor coil and the A/D converter may be of negligible length (and of negligible capacitance), and in any event may be shorter than a digital output cable between the A/D converter and the electronics.
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