公开(公告)号：WO2015097494A1

公开(公告)日：2015-07-02

申请号：PCT/IB2013/003083

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： KOSAREV, Nikolay ,  SHISHLOV, Sergey Y ,  IYER, Jayesh ,  BUTUZOV, Alexander ,  BABAYAN, Boris A. ,  KLUCHNIKOV, Andrey

IPC: G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3869

Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

Abstract translation: 处理器包括执行无序指令流的第一逻辑，划分成多个线的指令流，指令流和按程序顺序（PO）排序的每个线。 处理器还包括第二逻辑，用于确定指令流中最旧的未分配指令，并将最旧未分配指令的关联PO值存储为执行指令指针。 指令流包括调度和未分配的指令。 处理器还包括第三逻辑，用于确定指令流中最近退休的指令，并将最近退休的指令的相关联的PO值存储为退休指针;第四逻辑，用于选择退休指针和退出指令之间的指令范围; 执行指令指针，以及第五个逻辑，以标识符合退休条件的指令范围。

公开(公告)号：WO2015097493A1

公开(公告)日：2015-07-02

申请号：PCT/IB2013/003071

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： LECHENKO, Anton W ,  EFIMOV, Andrey ,  SHISHLOV, Sergey Y ,  IYER, Jayesh ,  BABAYAN, Boris A

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0842 ,  G06F9/3851 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0859 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/6042 ,  G06F2212/621

Abstract: A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation from an execution unit, respond to the memory operation with information from the data cache when the information is available in the data cache, and retrieve the information from the L2 cache when the information is unavailable in the data cache. The processor further includes logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor.

Abstract translation: 处理器包括Level-2（L2）高速缓存，第一和第二执行单元簇，以及通信地耦合到相应的执行单元集群和L2高速缓存的第一和第二数据高速缓存单元（DCU）。 DCU各自包括数据高速缓存和用于从执行单元接收存储器操作的逻辑，当信息在数据高速缓存中可用时，利用来自数据高速缓存的信息来响应存储器操作，并且当第二高速缓存中的信息从 信息在数据高速缓存中不可用。 所述处理器还包括将所述第一DCU的数据高速缓存的内容保持为等于所述第二DCU的数据高速缓存的内容的逻辑，所述内容在所述处理器的操作的所有时钟周期中。

公开(公告)号：WO2015145191A1

公开(公告)日：2015-10-01

申请号：PCT/IB2014/000621

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： LECHENKO, Anton ,  EFIMOV, Andrey ,  SHISHLOV, Sergey Y ,  KLUCHNIKOV, Andrey ,  GARIFULLIN, Kamil ,  BUROVENKO, Igor ,  BABAYAN, Boris A.

IPC: G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3857

Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.

Abstract translation: 处理器包括执行无序指令流的逻辑。 指令流被分成多个线，并且其指令和流内的指令按程序顺序（PO）排序。 处理器还包括用于识别指令流中最旧的未分配指令并将其相关联的PO记录为执行的指令指针的逻辑，识别指令流中最近提交的存储指令并将其关联的PO记录为存储承诺指针，搜索 具有PO的指针小于执行指令指针，在具有小于搜索指针的PO的存储缓冲器中识别第一组存储指令，并且有资格进行承诺，评估第一组存储指令是否大于读取端口的数量 存储缓冲区，并调整搜索指针。