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    BOOT STRAP PROCESSOR ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT
    1.
    发明申请
    BOOT STRAP PROCESSOR ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT 审中-公开
    用于多核处理单元的引导带处理器分配

    公开(公告)号：WO2013101086A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067885

    申请日：2011-12-29

    Applicant: INTEL CORPORATION ,  CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan Charan ,  MATAS, Ramon ,  LAWLOR, Jay, S. ,  NETTING, Robert, F.

    Inventor： CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan Charan ,  MATAS, Ramon ,  LAWLOR, Jay, S. ,  NETTING, Robert, F.

    IPC: G06F15/80 ,  G06F13/14

    CPC classification number: G06F9/4405 ,  G06F15/177

    Abstract: Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.

    Abstract translation: 在重新启动或重新启动包括多核处理器的系统之后，多核处理器可以将一个核心分配为引导带处理器（BSP）。 初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。 初始化逻辑可以检测多个处理核心中的每一个的属性被认定为被分配为BSP，或者不符合被分配为BSP的资格。 初始化逻辑可以至少部分地基于状态来检测作为活动处理核心的互连中的多个处理核心的最后处理核心，并且至少部分地基于属性被分配为BSP。 在各种实施例中，初始化信息可以将最后的处理核分配为BSP。

    EXTENDABLE CAMERA
    3.
    发明申请
    EXTENDABLE CAMERA 审中-公开
    可扩展相机

    公开(公告)号：WO2015148061A1

    公开(公告)日：2015-10-01

    申请号：PCT/US2015/018334

    申请日：2015-03-02

    Applicant: INTEL CORPORATION

    Inventor： THAKUR, Anshuman

    IPC: G03B17/56

    CPC classification number: H04N5/2251 ,  H04N5/2252

    Abstract: An extendable imager configured to capture an image responsive to a command from a mobile device and an arm coupled to the imager, the arm configured to extend the imager from a surface of the mobile device.

    Abstract translation: 可扩展成像器被配置为响应于来自移动设备的命令和耦合到成像器的臂来捕获图像，所述臂配置成从移动设备的表面延伸成像器。

    INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM
    5.
    发明申请
    INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM 审中-公开
    多核处理系统的初始化

    公开(公告)号：WO2013101093A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067900

    申请日：2011-12-29

    Applicant: INTEL CORPORATION ,  CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan Charan ,  MATAS, Ramon

    Inventor： CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan Charan ,  MATAS, Ramon

    IPC: G06F15/80 ,  G06F13/14

    CPC classification number: G06F9/4405 ,  G06F1/24 ,  G06F9/4403 ,  G06F11/0724 ,  G06F12/0813 ,  G06F13/00 ,  G06F13/14 ,  G06F15/177 ,  G06F15/80

    Abstract: This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.

    Abstract translation: 本公开涉及使用共享的初始化和配置向量，其被传递到使用分组的多核处理器中的处理核心。 初始化核心可以包括复位逻辑，其可以从集中存储位置读取初始化和配置向量，集中存储位置可以在包含处理核心（例如，熔丝等）的管芯上，例如在易失性存储器中， 闪存等），或两者的组合。 初始化内核然后可以生成分组以将初始化和配置向量传送到等待初始化（例如，重置之后）的处理核。 在一些情况下，初始化和配置向量信息可以由相同类型的两个或多个核共享。

    RESET OF MULTI-CORE PROCESSING SYSTEM
    6.
    发明申请
    RESET OF MULTI-CORE PROCESSING SYSTEM 审中-公开
    多核处理系统复位

    公开(公告)号：WO2013101077A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067864

    申请日：2011-12-29

    Applicant: INTEL CORPORATION ,  CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan charan ,  MATAS, Ramon

    Inventor： CHANG, Steven, S. ,  THAKUR, Anshuman ,  SUNDARARAMAN, Ramacharan charan ,  MATAS, Ramon

    IPC: G06F1/24 ,  G06F15/80 ,  G06F13/14

    CPC classification number: G06F1/24 ,  G06F1/3228 ,  G06F9/4405 ,  G06F13/14

    Abstract: An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.

    Abstract translation: 初始化核心可以包括可以检测全局复位信号（GRS）的复位逻辑。 初始化核心可以生成一个或多个能够与核心通信的分组。 初始化内核可以向指定内核执行复位的每个内核发送复位数据包。 在一些实施例中，复位命令可以关闭核心。 然后，初始化内核可以将未重新分配的数据包发送到指示内核执行未分配和上电的核心的每个核心。 在一些实施例中，核可以自动地恢复运行而不接收未重新分组。 分组的传输可以是交错的（分段）以控制处理器的上电，并且使处理器单元能够更慢地增加其功率状态。

    PROCESSING RECEIVE PROTOCOL DATA UNITS
    9.
    发明申请
    PROCESSING RECEIVE PROTOCOL DATA UNITS 审中-公开
    处理接收协议数据单元

    公开(公告)号：WO2006011963A1

    公开(公告)日：2006-02-02

    申请号：PCT/US2005/020551

    申请日：2005-06-10

    Applicant: INTEL CORPORATION (a Delaware Corporation) ,  COLMAN, Nicholas ,  KRISHNAN, Ramesh ,  THAKUR, Anshuman ,  CONE, Robert ,  MANSEAU, Daniel

    Inventor： COLMAN, Nicholas ,  KRISHNAN, Ramesh ,  THAKUR, Anshuman ,  CONE, Robert ,  MANSEAU, Daniel

    IPC: H04L12/56

    CPC classification number: H04L29/06 ,  H04L69/16 ,  H04L69/22

    Abstract: Provided are techniques for processing a data segment by stripping a header from a transport layer segment, performing protocol data unit detection to determine data for a protocol segment that is part of the transport layer segment data, and performing marker validation and stripping. Also provided are techniques for processing a data segment in which a header portion of a protocol data unit is received. A number of bytes of data to be stored in an application space is determined using the received header portion. Also, a next header portion of a next protocol data unit is determined using the received header portion. Then, a peek command is issued to obtain the next header portion. Additionally provided are techniques for performing cyclic redundancy checks using a stored partial cyclic redundancy check digest and residual data.

    Abstract translation: 提供了通过从传输层段剥离报头来处理数据段的技术，执行协议数据单元检测以确定作为传输层段数据的一部分的协议段的数据，以及执行标记验证和剥离。 还提供了用于处理其中接收到协议数据单元的报头部分的数据段的技术。 使用接收的报头部分来确定要存储在应用空间中的数据字节数。 此外，使用接收的报头部分来确定下一协议数据单元的下一报头部分。 然后，发出窥视命令以获得下一个标题部分。 另外提供了使用存储的部分循环冗余校验摘要和残差数据执行循环冗余校验的技术。

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