公开(公告)号：WO2006069197A2

公开(公告)日：2006-06-29

申请号：PCT/US2005/046482

申请日：2005-12-20

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke, S. ,  MURPHY, David

Inventor： REED, Coke, S. ,  MURPHY, David

IPC: G01R31/08 ,  H04L12/26 ,  H04L1/00 ,  H04L12/56 ,  H04L12/28

CPC classification number: H04L49/45 ,  H04L49/15 ,  H04L49/201 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/357

Abstract: An interconnect structure comprises a plurality of network-connected devices and a logic adapted to control a first subset of the network-connected devices to transmit data and simultaneously control a second subset of the network-connected devices to prepare for data transmission at a future time. The logic can execute an operation that activates a data transmission action upon realization of at least one predetermined criterion.

Abstract translation: 互连结构包括多个网络连接设备和适于控制网络连接设备的第一子集以发送数据并同时控制网络连接设备的第二子集的逻辑以准备将来的数据传输 。 逻辑可以执行在实现至少一个预定标准时激活数据传输动作的操作。

公开(公告)号：WO2005124577A3

公开(公告)日：2005-12-29

申请号：PCT/US2005/020701

申请日：2005-06-09

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke S. ,  MURPHY, David

Inventor： REED, Coke S. ,  MURPHY, David

IPC: G06F15/173

Abstract: In a system, a memory controller separates a memory into multiple banks (644) to be accessed concurrently. The memory controller further comprises a logic that creates a representation of a tree structure in memory and builds routing tables accessed by pointers at nodes in the tree memory structure, and a logic that finds a target memory address based on a received Internet Protocol (IP) address used by the tree memory structure and the routing table.

公开(公告)号：WO2007035437A2

公开(公告)日：2007-03-29

申请号：PCT/US2006/035914

申请日：2006-09-15

Applicant: INTERACTIC HOLDINGS LLC ,  REED, Coke ,  MURPHY, David

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/50

CPC classification number: H04L49/30 ,  H04L49/101 ,  H04L49/109 ,  H04L49/252

Abstract: An interconnect structure is disclosed comprising a collection of input ports, a collection of output ports, and a switching element. Data enters the switching element only at specific data entry times. The interconnect structure includes a collection of synchronizing elements. Data in the form of packets enter the input ports in an asynchronous fashion. The data packets pass from the input ports to the synchronizing units. The data exits the synchronizing units and enters the switching element with each packet arriving at the switching element at a specific data entry time.

Abstract translation: 公开了一种互连结构，其包括输入端口集合，输出端口集合和开关元件。 数据仅在特定的数据输入时间进入交换元件。 互连结构包括一组同步元件。 数据包形式的数据以异步方式进入输入端口。 数据包从输入端口传递到同步单元。 数据从同步单元退出并进入交换单元，每个数据包在特定的数据输入时间到达交换单元。

公开(公告)号：WO2020123796A1

公开(公告)日：2020-06-18

申请号：PCT/US2019/065967

申请日：2019-12-12

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke, S. ,  MURPHY, David ,  DENNY, Ronald, R. ,  IVES, Michael, R. ,  DEVANY, Reed

Inventor： REED, Coke, S. ,  MURPHY, David ,  DENNY, Ronald, R. ,  IVES, Michael, R. ,  DEVANY, Reed

IPC: H04L12/28 ,  H04L12/42 ,  H04L12/46 ,  H04L12/54 ,  H04L12/70 ,  H04L12/701 ,  H04L12/703

Abstract: Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data An interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. The Data Vortex switches are not crossbar switches, eliminating globally setting and resetting the Data Vortex switches as different groups of packets enter the switches. Mounting the Data Vortex switch on the same chip as the array of processing cores reduces power required and latency.

公开(公告)号：WO2005086912A2

公开(公告)日：2005-09-22

申请号：PCT/US2005/007940

申请日：2005-03-08

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke S. ,  MURPHY, David

Inventor： REED, Coke S. ,  MURPHY, David

IPC: H04L12/56

CPC classification number: H04L49/35 ,  H04L49/15 ,  H04L49/25 ,  H04L49/254 ,  H04L49/503

Abstract: A communication apparatus comprises a controlled switch capable of communicating scheduled messages and interfacing to a plurality of devices, and an uncontrolled switch capable of communicating unscheduled messages and interfacing to the plurality of devices. The uncontrolled switch generate signals that schedule the messages in the controlled switch.

Abstract translation: 通信装置包括能够传送调度消息并与多个设备接口的受控交换机，以及能够传送未调度消息并与多个设备接口的不受控制的交换机。 不受控制的交换机产生调度受控交换机中的消息的信号。

公开(公告)号：WO2005086791A2

公开(公告)日：2005-09-22

申请号：PCT/US2005/007488

申请日：2005-03-08

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke ,  MURPHY, David

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/56 ,  H04Q3/68

CPC classification number: H04Q3/68 ,  H04L12/18 ,  H04L49/101 ,  H04L49/15 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/254 ,  H04L49/3027 ,  H04L49/45 ,  H04L49/557 ,  H04L49/602

Abstract: An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device w the collection of devices from the second stage network exceeds the number of outputs from device w into the first stage network. The device w with N p input ports is capable of simultaneously receiving data from N p devices in the collection of devices. The latency through the entire system may be a fixed constant.

Abstract translation: 互连网络具有第一级网络和第二级网络以及网络外的设备集合，使得第一设备能够将数据发送到第二设备。 第一级网络连接到第二级网络的输入。 第一和第二级网络每个都具有比输入更多的输出。 数据首先从第一设备发送到第一级网络，然后从第一级网络发送到第二级网络。 数据从第二级网络发送到第二设备。 来自第二级网络的设备的收集的设备的输入数量超过从设备w进入第一级网络的输出的数量。 具有Np输入端口的设备w能够同时从设备集合中的Np设备接收数据。 整个系统的延迟可能是一个固定的常数。

公开(公告)号：WO2005043328A2

公开(公告)日：2005-05-12

申请号：PCT/US2004/036069

申请日：2004-10-27

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke, S. ,  MURPHY, David

Inventor： REED, Coke, S. ,  MURPHY, David

IPC: G06F

CPC classification number: H04L1/0072 ,  H04L1/0057 ,  H04L49/557

Abstract: An interconnect structure comprises a logic capable of error detection and/or error correction. A logic formats a data stream into a plurality of fixed-size segments. The individual segments include a header containing at least a set presence bit and a target address, a payload containing at least segment data and a copy of the target address, and a parity bit designating parity of the payload, the logic arranging the segment plurality into a multiple-dimensional matrix. A logic analyzes segment data in a plurality of dimensions following passage of the data through a plurality of switches including analysis to detect segment error, column error, and payload error.

Abstract translation: 互连结构包括能够进行错误检测和/或纠错的逻辑。 逻辑将数据流格式化成多个固定大小的段。 单个段包括包含至少一个设置的存在位和目标地址的标题，至少包含段数据和目标地址的副本，以及指定有效载荷的奇偶校验位的奇偶校验位，将该段多组合布置成 一个多维矩阵。 逻辑分析在数据通过包括分析的多个开关之后的多个维度中的段数据以检测段错误，列错误和有效负载错误。

公开(公告)号：WO2003090414A1

公开(公告)日：2003-10-30

申请号：PCT/US2003/011506

申请日：2003-04-15

Applicant: INTERACTICS HOLDING, LLC ,  REED, Coke, S. ,  MURPHY, David

Inventor： REED, Coke, S. ,  MURPHY, David

IPC: H04L12/50

CPC classification number: H04L49/103 ,  H04L49/101 ,  H04L49/205 ,  H04L49/254 ,  H04L49/3027

Abstract: An interconnect structure (200) comprising a plurality of input ports (204) and a plurality of output ports (252) with messages being sent from an input port to a predetermined output port through a switch S (210, 224). Advantageously, the setting of switch S is not dependent upon the predetermined output port to which a particular message is being sent.

Abstract translation: 一种互连结构（200），包括多个输入端口（204）和多个输出端口（252），其中消息通过开关S（210,224）从输入端口发送到预定的输出端口。 有利地，开关S的设置不依赖于正在发送特定消息的预定输出端口。

公开(公告)号：WO2004045172A1

公开(公告)日：2004-05-27

申请号：PCT/US2003/034894

申请日：2003-11-05

Applicant: INTERACTIC HOLDINGS, LLC

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/58

CPC classification number: H04L49/3072 ,  H04L49/1523 ,  H04L49/205 ,  H04L49/3018

Abstract: An interconnect structure (100) having a plurality of input ports and a plurality of output ports, including an input controller (150) which requests permission from predetermined logic within the structure to inject an entire message through two stages of data switches. The request contains only a portion of the address for a message target output with the amount of target output addresses supplied by the input controller (150) depending upon the data rate of the target output port.

Abstract translation: 具有多个输入端口和多个输出端口的互连结构（100），包括输入控制器（150），该输入控制器请求结构内的预定逻辑的许可以通过两级数据交换来注入整个消息。 该请求仅包含根据目标输出端口的数据速率的由输入控制器（150）提供的目标输出地址量的消息目标输出的地址的一部分。

公开(公告)号：WO2007116281A1

公开(公告)日：2007-10-18

申请号：PCT/IB2007/000847

申请日：2007-03-30

Applicant: NOKIA CORPORATION ,  NOKIA, INC. ,  SORVARI, Antti ,  MYLLYLÄ, Tomi ,  PAALASMAA, Joonas ,  MURPHY, David

Inventor： SORVARI, Antti ,  MYLLYLÄ, Tomi ,  PAALASMAA, Joonas ,  MURPHY, David

IPC: G10L17/00

CPC classification number: G10L17/00

Abstract: An apparatus for utilizing speaker recognition in content management includes an identity determining module. The identity determining module is configured to compare an audio sample which was obtained at a time corresponding to creation of a content item to stored voice models and to determine an identity of a speaker based on the comparison. The identity determining module is further configured to assign a tag to the content item based on the identity.

Abstract translation: 用于在内容管理中使用说话者识别的装置包括身份确定模块。 身份确定模块被配置为将与在内容项目的创建相对应的时间获得的音频样本与存储的语音模型进行比较，并且基于该比较来确定说话者的身份。 身份确定模块还被配置为基于身份将标签分配给内容项目。