公开(公告)号：WO2007035437A2

公开(公告)日：2007-03-29

申请号：PCT/US2006/035914

申请日：2006-09-15

Applicant: INTERACTIC HOLDINGS LLC ,  REED, Coke ,  MURPHY, David

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/50

CPC classification number: H04L49/30 ,  H04L49/101 ,  H04L49/109 ,  H04L49/252

Abstract: An interconnect structure is disclosed comprising a collection of input ports, a collection of output ports, and a switching element. Data enters the switching element only at specific data entry times. The interconnect structure includes a collection of synchronizing elements. Data in the form of packets enter the input ports in an asynchronous fashion. The data packets pass from the input ports to the synchronizing units. The data exits the synchronizing units and enters the switching element with each packet arriving at the switching element at a specific data entry time.

Abstract translation: 公开了一种互连结构，其包括输入端口集合，输出端口集合和开关元件。 数据仅在特定的数据输入时间进入交换元件。 互连结构包括一组同步元件。 数据包形式的数据以异步方式进入输入端口。 数据包从输入端口传递到同步单元。 数据从同步单元退出并进入交换单元，每个数据包在特定的数据输入时间到达交换单元。

公开(公告)号：WO2005086791A2

公开(公告)日：2005-09-22

申请号：PCT/US2005/007488

申请日：2005-03-08

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke ,  MURPHY, David

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/56 ,  H04Q3/68

CPC classification number: H04Q3/68 ,  H04L12/18 ,  H04L49/101 ,  H04L49/15 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/254 ,  H04L49/3027 ,  H04L49/45 ,  H04L49/557 ,  H04L49/602

Abstract: An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device w the collection of devices from the second stage network exceeds the number of outputs from device w into the first stage network. The device w with N p input ports is capable of simultaneously receiving data from N p devices in the collection of devices. The latency through the entire system may be a fixed constant.

Abstract translation: 互连网络具有第一级网络和第二级网络以及网络外的设备集合，使得第一设备能够将数据发送到第二设备。 第一级网络连接到第二级网络的输入。 第一和第二级网络每个都具有比输入更多的输出。 数据首先从第一设备发送到第一级网络，然后从第一级网络发送到第二级网络。 数据从第二级网络发送到第二设备。 来自第二级网络的设备的收集的设备的输入数量超过从设备w进入第一级网络的输出的数量。 具有Np输入端口的设备w能够同时从设备集合中的Np设备接收数据。 整个系统的延迟可能是一个固定的常数。

公开(公告)号：WO2003013061A1

公开(公告)日：2003-02-13

申请号：PCT/US2002/023411

申请日：2002-07-22

Applicant: INTERACTIC HOLDINGS, LLC ,  REED, Coke ,  HESSE, John

Inventor： REED, Coke ,  HESSE, John

IPC: H04L12/18

CPC classification number: H04L49/254 ,  H04L47/12

Abstract: This invention is directed to a parallel information generation, distribution and processing system (900). This scalable, pipelined control and switching system (900) efficiently and fairly manages a plurality of incoming data streams (132, 134), and applies class and quality of service requirements. The present invention also uses scalable MLML switch fabrics to control a data packet switch (930), including a request-processing switch (104) used to control the data-packet switch (930). Also included is a request processor (106) for each output port, which manages and approves all data flow to that output port, and an answer switch (108) which transmits answer packets from request processors (106) back to requesting input ports.

Abstract translation: 本发明涉及并行信息生成，分发和处理系统（900）。 这种可扩展的，流水线的控制和交换系统（900）有效和公平地管理多个输入数据流（132,134），并且应用类和服务质量要求。 本发明还使用可扩展的MLML交换结构来控制数据分组交换（930），包括用于控制数据分组交换（930）的请求处理交换机（104）。 还包括用于管理和批准到该输出端口的所有数据流的每个输出端口的请求处理器（106）和将请求处理器（106）的应答分组发送回请求输入端口的应答开关（108）。

公开(公告)号：WO2004045172A1

公开(公告)日：2004-05-27

申请号：PCT/US2003/034894

申请日：2003-11-05

Applicant: INTERACTIC HOLDINGS, LLC

Inventor： REED, Coke ,  MURPHY, David

IPC: H04L12/58

CPC classification number: H04L49/3072 ,  H04L49/1523 ,  H04L49/205 ,  H04L49/3018

Abstract: An interconnect structure (100) having a plurality of input ports and a plurality of output ports, including an input controller (150) which requests permission from predetermined logic within the structure to inject an entire message through two stages of data switches. The request contains only a portion of the address for a message target output with the amount of target output addresses supplied by the input controller (150) depending upon the data rate of the target output port.

Abstract translation: 具有多个输入端口和多个输出端口的互连结构（100），包括输入控制器（150），该输入控制器请求结构内的预定逻辑的许可以通过两级数据交换来注入整个消息。 该请求仅包含根据目标输出端口的数据速率的由输入控制器（150）提供的目标输出地址量的消息目标输出的地址的一部分。