公开(公告)号：WO2005088421A3

公开(公告)日：2006-03-16

申请号：PCT/IB2005050713

申请日：2005-02-28

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

Inventor： PESSOLANO FRANCESCO

IPC: G06F1/06 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/06

Abstract: A mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change) without spurious signals or glitches being created on the clock output line. A electronic device according to an exemplary embodiment, comprises a multiplexer (10) having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer (10) via a set of generic combinatorial delay elements (12) and the multiplexer output id fed to the output (Out) via an inverter (14). The element further comprises a D-type flip-flop (16) having as its "D" input a programming signal (Fk), and the two outputs "Q" and "Qn" from the D-type flip-flop provided respective drive signals to the multiplexer (10). The delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal (Fk), which is synchronized on the rising edge of the local clock (sync_ck).

Abstract translation: 一种用于产生集成电路或其一部分的时钟信号的机制，使得其频率可以在时钟输出线上不产生杂散信号或毛刺的情况下连续地（即逐渐变化的频率）安全地改变。 根据示例性实施例的电子设备包括具有两个输入信号的多路复用器（10），其中第二个是第一个的延迟版本，通过一组通用组合延迟将输入馈送到多路复用器（10）而产生 元件（12）和通过反相器（14）馈送到输出（Out）的多路复用器输出id。 该元件还包括具有作为其“D”输入编程信号（Fk）的D型触发器（16），并且提供来自D型触发器的两个输出“Q”和“Qn” 信号到多路复用器（10）。 输出信号（Out）相对于输入信号（In）的延迟取决于在本地时钟（sync_ck）的上升沿同步的编程信号（Fk）的值。

公开(公告)号：WO2005074138A3

公开(公告)日：2006-03-02

申请号：PCT/IB2005050245

申请日：2005-01-21

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

Inventor： PESSOLANO FRANCESCO

IPC: G06F1/08

CPC classification number: G06F1/08

Abstract: A clock generation circuit comprising two programmable ring oscillators (10, 20) arranged and configured to operate in a mutually exclusive manner, and a variable programmable delay element (not shown). An input programming pattern (14) is provided as an input to the oscillating circuit, the programming pattern (14) providing data representative of the sequence of frequencies at which the clock signal is required to be generated. The outputs of both the oscillators (10, 20) are connected to a clock switch (16), from which the generated clock signal (18) is output. When a request fro a change of frequency is received, the currently idle oscillator (20) is first activated with the next required frequency, the output of the currently operative oscillator (10) is then gated when the clock signal thereof goes low. Next, the previously gated output of oscillator (20) is ungated when its output goes low, and then oscillator (10) is de-activated.

Abstract translation: 一种时钟发生电路，包括布置和配置为以相互排斥的方式操作的两个可编程环形振荡器（10,20）和可变可编程延迟元件（未示出）。 输入编程模式（14）被提供给振荡电路的输入，编程模式（14）提供表示需要产生时钟信号的频率序列的数据。 两个振荡器（10,20）的输出端连接到时钟开关（16），输出所产生的时钟信号（18）。 当接收到频率变化的请求时，首先利用下一个所需频率激活当前空闲振荡器（20），当其工作时钟信号变低时，当前操作的振荡器（10）的输出被选通。 接下来，振荡器（20）的先前门控输出在其输出变为低电平时失谐，然后振荡器（10）被去激活。

公开(公告)号：WO2005073828A2

公开(公告)日：2005-08-11

申请号：PCT/IB2005050234

申请日：2005-01-20

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

Inventor： PESSOLANO FRANCESCO

IPC: G06F1/00 ,  G06F1/08

CPC classification number: G06F1/08

Abstract: A method of determining a maximum optimum clock frequency at which a digital processing system can operate, the method comprising the steps of: generating a clock signal at an initial frequency; increasing said frequency in a step-wise manner and determining the operation of said system each of a selected number of frequencies, until a clock frequency is identified at which said processor does not operate correctly; and identifying a maximum clock frequency at which said system can operate correctly; characterized in that: said maximum clock frequency comprises the frequency immediately previous to the one identified as being one at which said system does not operate correctly; and in that a timing monitor is provided for determining whether or not said system can operate within system timing constraints at each frequency, thereby indicating whether or not said system operates correctly at the respective frequency.

Abstract translation: 一种确定数字处理系统可操作的最大最佳时钟频率的方法，所述方法包括以下步骤：产生初始频率的时钟信号; 以逐步的方式增加所述频率并且确定所述系统的操作，每个频率选择一个频率，直到识别出所述处理器不正确地操作的时钟频率; 并且识别所述系统可以正确地操作的最大时钟频率; 其特征在于：所述最大时钟频率包括紧邻所述系统未正确操作的频率之前的频率; 并且提供了一种定时监视器，用于确定所述系统是否可以在每个频率的系统定时约束内操作，从而指示所述系统是否在相应频率下正确地操作。

公开(公告)号：WO2006097872A2

公开(公告)日：2006-09-21

申请号：PCT/IB2006050744

申请日：2006-03-09

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO ,  BARBIERI MAURO

Inventor： PESSOLANO FRANCESCO ,  BARBIERI MAURO

IPC: G11B20/10

CPC classification number: G11B20/10527 ,  G11B2020/10722

Abstract: The content reproduction system of the invention comprises storage means (3) for storing content, reproduction means (5) for reproducing the content, a buffer (7) coupled between the storage means and the reproduction means, a motion sensor (9) for sensing motion, and control circuitry (11) operative to configure the buffer's (7) size in dependence on the sensed motion. The method of the invention comprises the steps of reading content from a storage means into a buffer, reproducing content from the buffer using a reproduction means, sensing motion using a motion sensor, and configuring the buffer's size in dependence on the sensed motion.

Abstract translation: 本发明的内容再现系统包括用于存储内容的存储装置（3），用于再现内容的再现装置（5），耦合在存储装置和再现装置之间的缓冲器（7），用于感测的运动传感器 运动和控制电路（11），用于根据感测到的运动来配置缓冲器（7）的尺寸。 本发明的方法包括以下步骤：将内容从存储装置读入缓冲器，使用再现装置从缓冲器再现内容，使用运动传感器感测运动，以及根据所感测到的运动来配置缓冲器的大小。

公开(公告)号：WO2005006184A3

公开(公告)日：2006-03-09

申请号：PCT/IB2004051121

申请日：2004-07-05

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

Inventor： PESSOLANO FRANCESCO

IPC: G06F9/38

CPC classification number: G06F9/3848

Abstract: A system and method for predicting the outcome of a conditional branch within a computer system, the method comprising the steps of identifying (105) the occurrence of a conditional branch, obtaining (106) data relating to system activity since a previous branch, comparing (110) said data with data relating to previous system activity, and predicting (108) the branch outcome based on such comparison. An activity monitor (Figure 3 - 20) may be used to provide the data relating to system activity.

Abstract translation: 一种用于预测计算机系统内的条件分支的结果的系统和方法，所述方法包括以下步骤：识别（105）条件分支的出现，获得（106）与先前分支相关的系统活动的数据，比较（ 110）使用与先前系统活动相关的数据来表示数据，并且基于这样的比较来预测（108）分支结果。 活动监视器（图3-20）可用于提供与系统活动有关的数据。

公开(公告)号：WO2004027528A3

公开(公告)日：2004-08-05

申请号：PCT/IB0303568

申请日：2003-08-08

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

Inventor： PESSOLANO FRANCESCO

IPC: G05B19/00 ,  G05B19/042 ,  G05B19/418 ,  G06F9/38

CPC classification number: G05B19/00 ,  G06F9/3869 ,  G06F9/3871

Abstract: The present invention relates to a data processing circuitry and method of processing an input data pattern and outputting an output data pattern after a processing delay which depends on a processing activity of the data processing circuitry, wherein the processing delay is estimated based on the input pattern and the processing is controlled in response to the estimated processing delay. The processing control may be a power control based on an activity monitoring or a clock control in a pipeline structure. Thereby, an efficient solution is provided to derive the current activity of the processing circuitry in order to dynamically adapt its operating conditions to its demands.

Abstract translation: 本发明涉及处理输入数据模式并在取决于数据处理电路的处理活动的处理延迟之后输出输出数据模式的数据处理电路和方法，其中基于输入模式估计处理延迟 并且响应于估计的处理延迟来控制处理。 处理控制可以是基于流水线结构中的活动监视或时钟控制的功率控制。 因此，提供了一种有效的解决方案来导出处理电路的当前活动，以便动态调整其操作条件以满足其需求。

公开(公告)号：WO2006075287A3

公开(公告)日：2007-04-05

申请号：PCT/IB2006050083

申请日：2006-01-10

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J ,  HEIJLIGERS MARCUS J M

Inventor： PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J ,  HEIJLIGERS MARCUS J M

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A digital system 1 comprises receiving means (5) for receiving one or more performance indicators or parameters from software (6) controlling the execution of an application (3). Based on the performance indicators received by the receiving means (5), a tuning circuit (7) is provided for tuning the frequency (f), supply voltage (Vdd) and/or the transistor threshold voltage (Vb) of the digital system (1). In addition, pipeline configuration means (8) are provided for configuring the pipeline of the digital system (1) based on a pipeline depth determined by selecting means (10). The selecting means (10) is configured to select the pipeline depth (Pd) based on the frequency (f), supply voltage (Vdd), transistor threshold voltage (Vb), and according to whether the application requires maximum throughput or minimum latency.

Abstract translation: 数字系统1包括用于从控制应用程序（3）的执行的软件（6）接收一个或多个性能指示符或参数的接收装置（5）。 基于由接收装置（5）接收的性能指标，提供调谐电路（7），用于调谐数字系统的频率（f），电源电压（Vdd）和/或晶体管阈值电压（Vb） 1）。 此外，提供管线配置装置（8），用于基于由选择装置（10）确定的流水线深度来配置数字系统（1）的流水线。 选择装置（10）被配置为基于频率（f），电源电压（Vdd），晶体管阈值电压（Vb）以及根据应用是否需要最大吞吐量或最小等待时间来选择流水线深度（Pd）。

公开(公告)号：WO2005124516A3

公开(公告)日：2006-08-03

申请号：PCT/IB2005051894

申请日：2005-06-09

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J

Inventor： PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  PINEDA DE GYVEZ JOSE D J

IPC: G06F1/28 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The present invention relates to a method and circuit arrangement for controlling performance of an integrated circuit in response to a monitored performance indicator, wherein power supply of the integrated circuit is controlled based on said performance indicator. At least one of a noise level of the controlled power supply and a clock frequency generated in said integrated circuit is monitored and a respective control signal is fed back to the controlling function if the checking result is not within a predetermined range. Thereby, an simple and easily extendable automatic adaptation to process variations can be achieved.

Abstract translation: 本发明涉及一种用于响应于监视的性能指示器来控制集成电路的性能的方法和电路装置，其中基于所述性能指标来控制集成电路的电源。 如果检查结果不在预定范围内，则监控受控电源的噪声电平和在所述集成电路中产生的时钟频率中的至少一个，并且将相应的控制信号反馈到控制功能。 因此，可以实现简单且易于扩展的自动适应过程变化。

公开(公告)号：WO2004109531A3

公开(公告)日：2005-01-20

申请号：PCT/IB2004050799

申请日：2004-05-28

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PINEDA DE GYVEZ JOSE D J ,  PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  RIUS VAZQUEZ JOSEP ,  RAO KIRAN B R

Inventor： PINEDA DE GYVEZ JOSE D J ,  PESSOLANO FRANCESCO ,  MEIJER RINZE I M P ,  RIUS VAZQUEZ JOSEP ,  RAO KIRAN B R

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The present invention relates to real-time adaptive control for best Integrated Circuit (IC) performance. The adaptive behavior is carried out on a local basis. The system is partitioned into different islands (30). Each island (30) is controlled and its working conditions are modified depending on some parameters. The remainder of the chip is controlled as well, depending on other parameters. This requires that each island (30) has a local controller (36) communicating with a global controller (42). The main control parameters are e.g. supply voltage, threshold voltage and clock frequency.

Abstract translation: 本发明涉及用于最佳集成电路（IC）性能的实时自适应控制。 适应行为是在当地进行的。 系统被划分成不同的岛屿（30）。 每个岛（30）被控制，并且其工作条件根据一些参数而被修改。 芯片的其余部分也受到控制，取决于其他参数。 这要求每个岛（30）具有与全局控制器（42）通信的本地控制器（36）。 主要控制参数是例如。 电源电压，阈值电压和时钟频率。

公开(公告)号：WO2004095366A8

公开(公告)日：2004-12-09

申请号：PCT/IB2004050478

申请日：2004-04-21

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PESSOLANO FRANCESCO

Inventor： PESSOLANO FRANCESCO

IPC: G06K19/073 ,  H04L9/06 ,  G07F7/10

CPC classification number: G06K19/073 ,  G06K19/07363 ,  H04L9/003 ,  H04L2209/125

Abstract: The electronic circuit executes operations dependent on secret information. Power supply current dependency on the secret information is cloaked by drawing additional power supply current. A plurality of processing circuits (102, 106) executes respective parts of the operations dependent on the secret information. An activity monitor circuit (12a, b, 14), coupled to receive pairs of processing signals coming into and out of respective ones of the processing circuits, derive activity information from each pair of processing signals. The activity monitoring circuit (12a, b, 14) generates a combined activity signal indicative of a sum of power supply currents that will be consumed by the processing circuits (102, 106) dependent on the processing signals. A current drawing circuit connected to the power supply connections is controlled by the activity monitor circuit (12a, b, 14) to draw a cloaking current controlled by the combined activity signal, so that power supply current variations dependent on the secret information are cloaked in a sum of the cloaking current and current drawn by the processing circuits (102, 106).

Abstract translation: 电子电路执行取决于秘密信息的操作。 通过汲取额外的电源电流掩盖电源电流对秘密信息的依赖。 多个处理电路（102,106）执行取决于秘密信息的操作的各个部分。 被耦合以接收进出各个处理电路的处理信号对的活动监视电路（12a，b，14）从每对处理信号中导出活动信息。 活动监视电路（12a，b，14）根据处理信号产生指示将由处理电路（102,106）消耗的电源电流之和的组合活动信号。 连接到电源连接的电流绘图电路由活动监视电路（12a，b，14）控制以绘制由组合活动信号控制的隐藏电流，使得取决于秘密信息的电源电流变化隐藏在 由处理电路（102,106）汲取的隐形电流和电流的总和。