公开(公告)号：WO2006014395A3

公开(公告)日：2006-10-26

申请号：PCT/US2005023686

申请日：2005-07-01

Applicant: LATTICE SEMICONDUCTOR CORP

Inventor： VERNENKER HEMANSHU ,  TAIT MARGE ,  WHITE ALLEN

IPC: G11C7/10

CPC classification number: G11C7/1075 ,  G11C7/1039 ,  G11C7/1042

Abstract: Systems and methods are disclosed for memory, including techniques for reading and writing to memory. For example, in accordance with an embodiment of the present invention, a method of implementing a read and a write operation (e.g., a read before write operation) is disclosed for a memory, such as for example for a single port or a multiport memory, with the write operation beginning prior to the completion of the read operation.

Abstract translation: 公开了用于存储器的系统和方法，包括用于读取和写入存储器的技术。 例如，根据本发明的实施例，公开了一种实现读取和写入操作（例如，在写入操作之前的读取）的方法，用于存储器，例如对于单个端口或多端口存储器 写操作在读操作完成之前开始。

公开(公告)号：WO2007018661A3

公开(公告)日：2007-12-06

申请号：PCT/US2006018760

申请日：2006-05-12

Applicant: LATTICE SEMICONDUCTOR CORP

Inventor： DE LA CRUZ LOUIS ,  WHITE ALLEN ,  VERNENKER HEMANSHU

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: Systems and methods are disclosed herein to provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.

Abstract translation: 本文公开了系统和方法，以提供用于存储器的改进的地址解码技术。 例如，根据本发明的实施例，集成电路包括接收复位信号的地址寄存器，时钟信号和地址信号，并提供注册的地址信号。 登记的地址信号提供至少一个真实和补码信号，在确认复位信号时，将真实和补码信号设置为近似相同的逻辑值。 耦合到地址寄存器的地址预解码器至少部分地解码注册的地址信号以提供预解码的输出信号。 耦合到地址预解码器的字线驱动器接收字线使能信号和预解码输出信号，并且在断言字线使能信号时，基于预解码的输出信号提供字线信号。

公开(公告)号：WO2006047089A3

公开(公告)日：2006-07-27

申请号：PCT/US2005036590

申请日：2005-10-07

Applicant: LATTICE SEMICONDUCTOR CORP

Inventor： SWENSEN TIM ,  TSAI SAM ,  EPLETT STEVE ,  HUME CHRISTOPHER ,  TAIT MARGE ,  VERNENKER HEMANSHU ,  WHITE ALLEN

IPC: G11C11/34 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/103 ,  G11C7/1066

Abstract: Systems and methods provide output data from a memory. For example, in accordance with an embodiment of the present invention, techniques are disclosed for providing glitch-free output data from a memory through feedback of the output data signal.

Abstract translation: 系统和方法从存储器提供输出数据。 例如，根据本发明的实施例，公开了用于通过输出数据信号的反馈从存储器提供无毛刺输出数据的技术。

公开(公告)号：WO2006017461A2

公开(公告)日：2006-02-16

申请号：PCT/US2005027325

申请日：2005-08-02

Applicant: LATTICE SEMICONDUCTOR CORP

Inventor： VERNENKER HEMANSHU ,  TAIT MARGE ,  WHITE ALLEN ,  HUME CHRISTOPHER

IPC: G11C8/00

CPC classification number: G11C8/16

Abstract: Systems and methods are disclosed herein to provide techniques for writing to certain bits of a word location in a memory. For example, in accordance with an embodiment of the present invention, a method of implementing byte enable logic for a memory is disclosed, with the byte enable logic signals provided on one or more address lines.

Abstract translation: 本文公开了系统和方法以提供用于写入存储器中的单词位置的某些位的技术。 例如，根据本发明的实施例，公开了一种用于存储器的字节使能逻辑的方法，其中在一个或多个地址线上提供字节使能逻辑信号。