公开(公告)号：WO2023284177A1

公开(公告)日：2023-01-19

申请号：PCT/CN2021/128174

申请日：2021-11-02

申请人： 长鑫存储技术有限公司

发明人： 陈继兴 ,  尚为兵

IPC分类号： G11C29/00 ,  G11C11/34

摘要： 本申请实施例提供一种半导体存储器及其上存储块的容量配置方法，其中，所述方法包括：确定存储器上的待配置的目标存储块；确定目标存储块的容量配置参数，从目标存储块的一组编码中，确定目标编码；目标编码对应目标存储块中待修剪的存储区域；基于目标编码，生成用于选中目标存储块中待修剪的存储区域的区域选择信号；基于区域选择信号，对待修剪的存储区域进行修剪，以实现对目标存储块的容量进行配置。本申请能够灵活选取待修剪的存储区域，提升对半导体存储器上存储块的容量配置的有效利用率。

公开(公告)号：WO2021050984A1

公开(公告)日：2021-03-18

申请号：PCT/US2020/050544

申请日：2020-09-11

申请人： HEFEI RELIANCE MEMORY LIMITED

发明人： MANEA, Danut

IPC分类号： G11C11/21 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/40 ,  G11C11/34 ,  G11C5/14

摘要： Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.

公开(公告)号：WO2020150810A1

公开(公告)日：2020-07-30

申请号：PCT/CA2020/050053

申请日：2020-01-17

申请人： MILLER, Mitchell

发明人： MILLER, Mitchell

IPC分类号： G11C11/34 ,  G11C11/4193

摘要： A system and method for bidirectionally based electrical information storage, processing and communication. Bidirectional memory (tristate) offers the capability to store and interpret multiple bits (Shannon's) of information per memory cell, for structures such as dynamic random-access memory (DRAM), and read-only memory (ROM), and communication circuits, for operation, rather than traditional memory able to store a single "bit" (Shannon) of information per cell. Where, instead of traditional memory cells capable of two possible states (binary digit) and a single defined bit (1 Shannon), bidirectional memory is capable of three states (tristate), where the third information representing state can be a specifically defined state capable of representing multiple bits (multiple Shannon's) for each individual cell, which may be defined to represent a specific sequence of bits (sequence of Shannon's). Additionally, the 3 rd information state of a tristate bidirectional memory cell may be expressed as in a state of constant variability (superposition), where the final determined state may be based on a probabilistic outcome, or probability controlled. The disclosed system and method allows for more complex systems for information storage, compression, processing, communication, and more secure encryption of stored or communicated information.

公开(公告)号：WO2020132152A1

公开(公告)日：2020-06-25

申请号：PCT/US2019/067298

申请日：2019-12-18

申请人： NORTHEASTERN UNIVERSITY

发明人： HENNIGHAUSEN, Zachariah Boston ,  KAR, Swastik

IPC分类号： C23C14/16 ,  H01L21/02 ,  H01L29/786 ,  H01L31/0232 ,  H01L31/12 ,  G11C11/34

摘要： 2D heterostructures comprising Bi 2 Se 3 /MoS 2 , Bi 2 Se 3 /MoSe 2 , Bi 2 Se 3 /WS 2 , Bi 2 Se 3 /MoSe 2 . 2x S 2x, or mixtures thereof in which oxygen is intercalated between the layers at selected positions provide high density storage devices, sensors, and display devices. The properties of the 2D heterostructures can be configured utilizing a beam of electromagnetic waves or particles in an oxygen controlled atmosphere.

公开(公告)号：WO2017070018A1

公开(公告)日：2017-04-27

申请号：PCT/US2016/057101

申请日：2016-10-14

申请人： SILICON STORAGE TECHNOLOGY, INC.

发明人： CHEN, Chun-Ming ,  WU, Man-Tang ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  DO, Nhan

IPC分类号： G11C16/02 ,  G11C11/34 ,  G06F13/00

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

摘要： A method of forming a non- volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

摘要翻译： 形成非易失性存储器单元的方法包括在衬底中形成间隔开的第一区域和第二区域，在其间限定沟道区域。 浮置栅极形成在沟道区域的第一部分之上以及第一区域的一部分之上，其中浮置栅极包括布置在第一区域之上的尖锐边缘。 隧道氧化层围绕尖锐边缘形成。 擦除栅极形成在第一区域上方，其中擦除栅极包括面向尖锐边缘的凹口，并且其中凹口通过隧道氧化物层与尖锐边缘绝缘。 字线门形成在与第二区域相邻的沟道区域的第二部分之上。 字线门的形成是在形成隧道氧化层和擦除门之后进行的。

公开(公告)号：WO2017058347A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/044336

申请日：2016-07-27

申请人： HARARI, Eli

发明人： HARARI, Eli

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  H01L29/792

CPC分类号： G11C16/3431 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： Multi-gate NOR flash thin-film transistor (TFT) string arrays ("multi-gate NOR string arrays") are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

摘要翻译： 多栅极NOR闪存薄膜晶体管（TFT）串阵列（“多栅极NOR串阵列”）被组织为平行于硅衬底的表面延伸的水平有源条的堆叠，每个堆叠中的TFT被控制 通过沿着活动条的堆叠的一个或两个侧壁设置的垂直的局部字线。 每个有源条带至少包括在两个共用源极或漏极层之间形成的沟道层。 有源条带的TFT中的数据存储由提供在有源条和由相邻本地字线提供的控制栅之间的电荷存储元件提供。 取决于使用活动条的一侧还是两侧，每个活动条可以提供属于一个或两个NOR字符串的TFT。

公开(公告)号：WO2017044338A1

公开(公告)日：2017-03-16

申请号：PCT/US2016/049286

申请日：2016-08-29

申请人： CYPRESS SEMICONDUCTOR CORPORATION

发明人： AGRAWAL, Vineet ,  BETTMAN, Roger ,  LESHNER, Samuel

IPC分类号： G06F12/02 ,  G11C11/21 ,  G11C11/34 ,  G11C16/02 ,  G11C16/04

CPC分类号： G11C7/18 ,  G06F12/023 ,  G06F2212/1044 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1015 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line.. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

摘要翻译： 这里公开了用于并行读写操作的系统，方法和装置。 设备可以包括耦合到本地位线的第一传输设备和与存储器阵列的存储器单元相关联的全局位线。 第一传输设备可以被配置为选择性地将全局位线耦合到本地位线。设备还可以包括耦合到本地位线的第一设备和读出放大器。 第一器件可以被配置为选择性地将局部位线耦合到读出放大器。 该装置还可以包括耦合到本地位线和电接地的第二装置。 第二装置可以被配置为选择性地将局部位线耦合到电接地。

公开(公告)号：WO2016168123A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/026986

申请日：2016-04-11

申请人： NEO SEMICONDUCTOR, INC.

发明人： HSU, Fu-Chang

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  H01L21/336 ,  H01L21/8236 ,  H01L27/06

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0886 ,  H01L27/11206 ,  H01L27/1211

摘要： A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N- well and an anti-fuse cell formed on the N- well. The anti-fuse cell includes a drain P+ diffusion deposited in the N- well, a source P+ diffusion deposited in the N- well, and an oxide layer deposited on the N- well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

摘要翻译： 公开了一种CMOS反熔丝单元。 一方面，一种装置包括形成在N阱上的N阱和反熔丝单元。 反熔丝单元包括沉积在N阱中的漏极P +扩散层，沉积在N阱中的源极P +扩散层，以及沉积在N-阱上并且具有与漏极P +扩散重叠的重叠区域的氧化物层。 控制栅极沉积在氧化物层上。 当控制栅极和漏极P +扩散之间的电压差超过氧化物层的电压阈值并形成从控制栅极到漏极P +扩散的泄漏路径时，抗熔丝单元的数据位被编程。 泄漏路径被限制在重叠区域中。

公开(公告)号：WO2016118381A1

公开(公告)日：2016-07-28

申请号：PCT/US2016/013258

申请日：2016-01-13

申请人： CYPRESS SEMICONDUCTOR CORPORATION

发明人： ASHOKKUMAR, Jayant ,  RAGHAVAN, Vijay ,  PRABHAKAR, Venkatraman ,  SAHA, Swatilekha

IPC分类号： G11C11/34

CPC分类号： G11C16/14 ,  G11C11/2275 ,  G11C14/00 ,  G11C14/0063 ,  G11C14/0072 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483

摘要： A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

摘要翻译： 提供包括非易失性锁存（NVL）单元阵列的存储器及其操作方法。 在一个实施例中，每个NVL单元包括非易失性部分和易失性部分。 非易失性部分包括第一非易失性存储器（NVM）器件和串联耦​​合在第一输出节点和位线真之间的第一非易失性存储器（NVM）器件和第一通过栅极晶体管，以及串联耦合的第二NVM器件和第二通过栅极晶体管 第二输出节点和位线补码。 易失性部分包括交叉耦合的第一和第二场效应晶体管（FET），耦合在电源电压（VPWR）和第一输出节点之间的第一FET以及耦合在VPWR和第二输出节点之间的第二FET。 第一FET的栅极耦合到第二输出节点，并且第二FET的栅极耦合到第一输出节点。

公开(公告)号：WO2015147817A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/031907

申请日：2014-03-26

申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

发明人： VOIGT, Douglas L.

IPC分类号： G11C11/34

CPC分类号： G06F9/4401 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0637 ,  G06F3/0652 ,  G06F3/0688 ,  G06F9/4418 ,  G06F12/1408 ,  G06F12/1458 ,  G06F2212/1052 ,  G06F2212/402 ,  G11C16/20

摘要： A property is determined of an object in nonvolatile memory (NVM) of a device after the device is restarted. An action is performed on the NVM object based on the determined property of the NVM object. The property includes at least one of a volatility and executable information of the NVM object.

摘要翻译： 在设备重新启动后，确定设备的非易失性存储器（NVM）中的对象的属性。 基于所确定的NVM对象的属性，对NVM对象执行操作。 该属性包括NVM对象的易失性和可执行信息中的至少一个。