公开(公告)号：WO0116999A2

公开(公告)日：2001-03-08

申请号：PCT/US0023503

申请日：2000-08-25

Applicant: MACRONIX AMERICA INC

Inventor： LU TAO CHENG ,  TSAI WEN-JER ,  CHANG YAO WEN ,  WANG MAM TSUNG

IPC: G11C11/56 ,  H01L

CPC classification number: G11C11/5692 ,  G11C11/56

Abstract: A method of providing a multilevel programmed Mask ROM that begins by fabricating an unprogrammed mask ROM. The transistors in the mask ROM array are programmed with one of a plurality of threshold voltages using low concentration ion implantation. The method minimizes the leakage current during reading of the array from at least the transistors programmed with a first level threshold voltage. Minimization of leakage current includes biasing at least the first level threshold voltage programmed transistors by applying a negative voltage to the gates of those transistors, implanting at least standard ion implantation dosages in regions surrounding the first level threshold voltage programmed transistors, or by selecting an inhibiting source voltage that substantially eliminates leakage current from at least the first level threshold voltage programmed transistors and then reading the array by applying the inhibiting source voltage to the sources and the inhibiting source voltage plus approximately 1.2V to the drains of the transistors.

Abstract translation: 一种提供多级编程掩模ROM的方法，该方法从制造未编程的掩模ROM开始。 使用低浓度离子注入用多个阈值电压中的一个对掩模ROM阵列中的晶体管进行编程。 该方法在从至少用第一电平阈值电压编程的晶体管读取阵列期间最小化泄漏电流。 最小化泄漏电流包括通过向这些晶体管的栅极施加负电压，至少在第一级阈值电压编程晶体管周围的区域中注入标准离子注入剂量，或者通过选择抑制 源电压基本上消除至少来自第一电平阈值电压编程的晶体管的泄漏电流，然后通过将抑制源电压施加到源并且将抑制源电压加上大约1.2V加上晶体管的漏极来读取阵列。