公开(公告)号：WO2015153060A1

公开(公告)日：2015-10-08

申请号：PCT/US2015/019227

申请日：2015-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  CHEN, Wei-Chuan ,  KANG, Seung Hyuk ,  LEE, Kangho

IPC: G11C13/00 ,  G11C17/16 ,  G11C11/56 ,  G11C11/00

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C11/5614 ,  G11C11/5685 ,  G11C11/5692 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C17/165 ,  G11C2013/0042

Abstract: An anti-fuse device includes a first electrode, an insulator on the first electrode, a second electrode on the insulator, and selector logic coupled to the second electrode. The device also includes a conductive path between the first and second electrodes. The conductive path may be configured to provide a hard breakdown for one-time programmable non-volatile data storage.

Abstract translation: 反熔丝器件包括第一电极，第一电极上的绝缘体，绝缘体上的第二电极以及耦合到第二电极的选择器逻辑。 该装置还包括在第一和第二电极之间的导电路径。 导电路径可以被配置为提供一次性可编程非易失性数据存储器的硬击穿。

公开(公告)号：WO2007126669A1

公开(公告)日：2007-11-08

申请号：PCT/US2007/007109

申请日：2007-03-22

Applicant: SANDISK 3D LLC ,  HERNER, Brad, S.

Inventor： HERNER, Brad, S.

IPC: H01L27/24 ,  H01L45/00

CPC classification number: G11C11/5685 ,  G11C11/5692 ,  G11C13/0007 ,  G11C17/16 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1675

Abstract: A nonvolatile memory cell includes a layer (118) of a resistivity-switching metal oxide or nitride compound, the metal oxide or nitride compound including one metal, and a dielectric rupture antifuse (117) formed in series. The dielectric rupture antifuse may be either in its initial, non-conductive state or a ruptured, conductive state. The resistivity-switching metal oxide or nitride layer can be in a higher- or lower-resistivity state. By using both the state of the resistivity- switching layer and the antifuse to store data, more than two bits can be stored per memory cell.

Abstract translation: 非易失性存储单元包括电阻率切换金属氧化物或氮化物化合物的层（118），包括一种金属的金属氧化物或氮化物化合物和串联形成的介电破裂反熔丝（117）。 介电破裂反熔丝可以处于其初始，非导通状态或破裂的导电状态。 电阻率切换金属氧化物或氮化物层可以处于较高或较低电阻率的状态。 通过使用电阻率切换层的状态和反熔丝来存储数据，每个存储单元可以存储两个以上的位。

公开(公告)号：WO00030118A1

公开(公告)日：2000-05-25

申请号：PCT/US1999/009471

申请日：1999-04-29

IPC: H01L27/10 ,  G11C11/56 ,  G11C17/16 ,  H01L27/102 ,  G11C13/00 ,  G11C11/22 ,  G11C17/00

CPC classification number: H01L27/1021 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/76

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers (51a1, 51a2, 51b2), each layer (51a1) of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract translation: 公开了一种非常高密度的现场可编程存储器。 使用几层（51a1,51a2,5bb2）在衬底上方垂直地形成阵列，其每层（51a1）包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。 自动对准技术的最大限度地使光刻限制最小化。 在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

公开(公告)号：WO99014762A1

公开(公告)日：1999-03-25

申请号：PCT/NO1998/000263

申请日：1998-08-28

IPC: G11C16/04 ,  G11C20060101 ,  G11C11/56 ,  G11C17/06 ,  G11C17/10 ,  H01L20060101 ,  H01L27/02 ,  H01L27/10 ,  H01L27/102 ,  H01L27/112 ,  H01L27/28 ,  H01L51/05

CPC classification number: G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5692 ,  G11C13/0016 ,  H01L27/112

Abstract: A read-only memory is made electrically addressable over a passive conductor matrix, wherein the volume between intersection of two conductors (2; 4) in the matrix defines a memory cell (5). Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2; 4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code. One or more read-only memories (ROM) may be provided on a semiconductor substrate (1) which also comprises driver and control circuits (13), to accomplish a read-only memory device. The device may be realized either planar or also volumetrically by stacking several read-only memories (ROM) in horizontal layers (15) and connecting them with the substrate (1) via addressing buses.

Abstract translation: 只读存储器在无源导体矩阵上可电寻址，其中矩阵中两个导体（2; 4）的相交之间的体积限定了存储单元（5）。 数据作为阻抗值存储在存储单元中。 存储单元（5）包括提供高阻抗的隔离材料（6）或一个或多个无机或有机半导体（9），优选具有各向异性导电性能。 半导体材料（9）在与基体中的金属导体（2; 4）的界面处形成二极管结。 通过分别将存储单元中的隔离材料（6）和半导体材料（9）适当地布置，这些可以被给予确定的阻抗值，其可以被电读取并对应于二值或多值代码中的逻辑值。 可以在也包括驱动器和控制电路（13）的半导体衬底（1）上提供一个或多个只读存储器（ROM），以实现只读存储器件。 该装置可以通过在水平层（15）中堆叠几个只读存储器（ROM）并且经由寻址总线将其与衬底（1）连接来实现平面或体积式地实现。

公开(公告)号：WO2009072103A2

公开(公告)日：2009-06-11

申请号：PCT/IL2008001233

申请日：2008-09-17

Applicant: DENSBITS TECHNOLOGIES LTD ,  WEINGARTEN HANAN ,  LEVY SHMUEL ,  KATZ MICHAEL

Inventor： WEINGARTEN HANAN ,  LEVY SHMUEL ,  KATZ MICHAEL

IPC: G06F12/02

CPC classification number: G06F11/1044 ,  G06F11/1068 ,  G11C11/5621 ,  G11C11/5692 ,  G11C29/00

Abstract: A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.

Abstract translation: 一种用于对作为单元进行纠错编码的多个闪存单元进行解码的方法，所述方法包括提供硬解码成功指示，指示硬解码是否至少可能成功; 以及仅当所述硬解码成功指示指示所述硬解码最不可能成功时，以所述第一分辨率对所述多个闪存单元进行软解码。

公开(公告)号：WO2009002476A2

公开(公告)日：2008-12-31

申请号：PCT/US2008/007801

申请日：2008-06-23

Applicant: SANDISK 3D LLC ,  HERNER, S., Brad ,  CLARK, Mark, H. ,  KUMAR, Tanmay

Inventor： HERNER, S., Brad ,  CLARK, Mark, H. ,  KUMAR, Tanmay

IPC: H01L27/102 ,  H01L29/868 ,  G11C11/36 ,  H01L29/861 ,  H01L29/161 ,  H01L29/167 ,  H01L29/26

CPC classification number: H01L29/868 ,  G11C11/5692 ,  G11C17/06 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/0688 ,  H01L27/1021 ,  H01L29/04 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66136 ,  H01L29/8615

Abstract: A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.

Abstract translation: 非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管，其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。

公开(公告)号：WO2008016421A2

公开(公告)日：2008-02-07

申请号：PCT/US2007/013772

申请日：2007-06-12

Applicant: SANDISK 3D LLC ,  SCHEUERLEIN, Roy, E. ,  PETTI, Christopher, J.

Inventor： SCHEUERLEIN, Roy, E. ,  PETTI, Christopher, J.

IPC: G11C13/02

CPC classification number: G11C17/165 ,  G11C11/56 ,  G11C11/5692 ,  G11C13/0002 ,  G11C17/16 ,  G11C29/76 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2213/72

Abstract: A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X≠Y.

Abstract translation: 公开了具有不同数据状态的混合使用存储器阵列及其使用方法。 在一个优选实施例中，提供包括多个存储单元的存储器阵列，每个存储单元包括存储元件，存储元件包括可配置为至少三个电阻率状态之一的可切换电阻材料。 第一组存储器单元使用X电阻率状态来表示X个相应的数据状态，并且第二组存储器单元使用Y电阻率状态来表示Y个相应的数据状态，其中X≥Y。

公开(公告)号：WO2007001855A3

公开(公告)日：2007-05-31

申请号：PCT/US2006023121

申请日：2006-06-13

Applicant: FREESCALE SEMICONDUCTOR INC ,  ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

Inventor： ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K

IPC: H01L21/336

CPC classification number: G11C17/18 ,  G11C11/1673 ,  G11C11/1695 ,  G11C11/5692 ,  G11C17/02

Abstract: A patterned polysilicon gate (18) is over a metal layer (16) that is over a gate dielectric layer (14), which in turn is over a semiconductor substrate (12). A thin layer (20) of material is conformally deposited over the polysilicon gate (18) and the exposed metal layer (16) and then etched back to form a sidewall spacer (22) on the polysilicon gate (18) and to re-expose the previously exposed portion of the metal layer (16). The re-exposed metal layer (16) is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer (22). Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate (18) but for the protection provided by the sidewall spacer (22). After the re-exposed metal (16) has been removed, a transistor is formed in which the metal layer (14,24) sets the work function of the gate of the transistor.

Abstract translation: 图案化多晶硅栅极（18）位于栅极电介质层（14）之上的金属层（16）的上方，栅极电介质层又在半导体衬底（12）上。 材料的薄层（20）共形沉积在多晶硅栅极（18）和暴露的金属层（16）上，然后被回蚀刻以在多晶硅栅极（18）上形成侧壁间隔物（22）并重新暴露 金属层（16）的先前曝光的部分。 使用对栅极介电材料和侧壁间隔物（22）选择性的蚀刻剂来蚀刻再曝光的金属层（16）。 尽管这种蚀刻基本上是各向异性的，但是它具有各向同性的成分，其蚀刻多晶硅栅极（18）的侧壁，但是用于由侧壁间隔物（22）提供的保护。 在再暴露的金属（16）已经被去除之后，形成晶体管，其中金属层（14,24）设置晶体管的栅极的功函数。

公开(公告)号：WO2007001855A2

公开(公告)日：2007-01-04

申请号：PCT/US2006/023121

申请日：2006-06-13

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

Inventor： ANDRE, Thomas W. ,  SUBRAMANIAN, Chitra K.

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C11/1673 ,  G11C11/1695 ,  G11C11/5692 ,  G11C17/02

Abstract: A patterned polysilicon gate (18) is over a metal layer (16) that is over a gate dielectric layer (14), which in turn is over a semiconductor substrate (12). A thin layer (20) of material is conformally deposited over the polysilicon gate (18) and the exposed metal layer (16) and then etched back to form a sidewall spacer (22) on the polysilicon gate (18) and to re-expose the previously exposed portion of the metal layer (16). The re-exposed metal layer (16) is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer (22). Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate (18) but for the protection provided by the sidewall spacer (22). After the re-exposed metal (16) has been removed, a transistor is formed in which the metal layer (14,24) sets the work function of the gate of the transistor.

Abstract translation: 图案化多晶硅栅极（18）位于栅极电介质层（14）上的金属层（16）上方，该栅极电介质层（14）又位于半导体衬底（12）上方。 在多晶硅栅极（18）和暴露的金属层（16）上共形地沉积材料薄层（20），然后回蚀刻以在多晶硅栅极（18）上形成侧壁间隔物（22）并重新曝光 之前暴露的金属层（16）部分。 使用对栅极电介质材料和侧壁间隔物（22）有选择性的蚀刻剂来蚀刻重新暴露的金属层（16）。 尽管这种蚀刻基本上是各向异性的，但它具有各向同性的成分，其将蚀刻多晶硅栅极（18）的侧壁，但是用于由侧壁间隔物（22）提供的保护。 在重新暴露的金属（16）已经被去除之后，形成晶体管，其中金属层（14,24）设置晶体管的栅极的功函数。

公开(公告)号：WO2005112119A1

公开(公告)日：2005-11-24

申请号：PCT/US2005/015624

申请日：2005-05-04

Applicant: MICRON TECHNOLOGY, INC. ,  FORBES, Leonard

Inventor： FORBES, Leonard

IPC: H01L27/115

CPC classification number: H01L27/115 ,  G11C11/5692 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/10 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: An array of NROM flash memory cells configured to store at least two bits per four F 2 . Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The split channels can be connected by an n+ region at the bottom of the trench or the channel wrapping around the trench bottom. Each gate insulator is capable of storing a charge that is adequately separated from the other charge storage area due to the increased channel length.

Abstract translation: NROM闪存单元的阵列被配置为每四个F 2存储至少两个比特。 沿相邻支柱的每一侧产生分割垂直通道。 在支柱之间和柱之间的沟槽中形成单个控制门。 分裂通道可以通过沟槽底部的n +区域或围绕沟槽底部的通道连接。 每个栅极绝缘体能够存储由于增加的沟道长度而与其它电荷存储区域充分分离的电荷。