公开(公告)号：WO2017197215A1

公开(公告)日：2017-11-16

申请号：PCT/US2017/032321

申请日：2017-05-12

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： SENAPATI, Ashish ,  STEEDMAN, Sean ,  LOERTSCHER, Brent

IPC: G06F9/34

Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

Abstract translation: 一个8位微处理器具有一个具有16位指令字大小的程序存储器和一个具有8位数据大小的数据存储器。 一个指令字的地址有效载荷大小为12位。 此外，微处理器具有与程序存储器和数据存储器耦合的中央处理单元，被配置为选择多达64个存储体中的一个的存储体选择寄存器以及可操作来寻址高达16KB数据存储器的间接寻址寄存器。 CPU被配置为执行具有两个指令字并被配置为仅访问数据存储器的较低4KB的第一移动指令和具有三个指令字并被配置为访问整个数据存储器的第二移动指令。