公开(公告)号：WO2014082029A1

公开(公告)日：2014-05-30

申请号：PCT/US2013/071631

申请日：2013-11-25

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： STEEDMAN, Sean ,  DUVENHAGE, Fanie

IPC: G06F1/08

CPC classification number: G06F1/08

Abstract: A microcontroller has a numerical controlled oscillator receiving a primary clock signal and is configured to provide an internal system clock of the microcontroller. A method for operating a microcontroller performs the following steps: Selecting a primary clock signal from a plurality of clock signals; feeding the primary clock signal to a numerical controlled oscillator; configuring the numerical controlled oscillator to generate a numerical controlled clock signal; and providing the numerical controlled clock signal as an internal system clock for the microcontroller.

Abstract translation: 微控制器具有接收主时钟信号的数控振荡器，并被配置为提供微控制器的内部系统时钟。 一种用于操作微控制器的方法执行以下步骤：从多个时钟信号中选择主时钟信号; 将主时钟信号馈送到数控振荡器; 配置数控振荡器以产生数字控制的时钟信号; 并提供数字控制时钟信号作为微控制器的内部系统时钟。

公开(公告)号：WO2010093661A2

公开(公告)日：2010-08-19

申请号：PCT/US2010/023706

申请日：2010-02-10

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  LUNDSTRUM, Zeke, R. ,  DELPORT, Vivien ,  STEEDMAN, Sean ,  JULICHER, Joseph

Inventor： LUNDSTRUM, Zeke, R. ,  DELPORT, Vivien ,  STEEDMAN, Sean ,  JULICHER, Joseph

IPC: G06F9/30

CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/35 ,  G06F12/0623

Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.

Abstract translation: 一种用于具有划分成多个存储体的数据存储器的微控制器的指令集，其中数据存储器具有多个存储体的多于一个存储体，其形成没有特殊功能寄存器映射的线性数据存储器块， 没有映射到用于选择存储体的数据存储器并且映射到至少一个存储体的间接访问寄存器的存储体选择寄存器，其中指令集包括可以直接寻址一个存储体内的所有存储器位置的多个指令 至少一个提供对存储体选择寄存器的访问的指令，以及使用间接访问寄存器向数据存储器执行间接地址的至少一个指令。

公开(公告)号：WO2017197215A1

公开(公告)日：2017-11-16

申请号：PCT/US2017/032321

申请日：2017-05-12

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： SENAPATI, Ashish ,  STEEDMAN, Sean ,  LOERTSCHER, Brent

IPC: G06F9/34

Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

Abstract translation: 一个8位微处理器具有一个具有16位指令字大小的程序存储器和一个具有8位数据大小的数据存储器。 一个指令字的地址有效载荷大小为12位。 此外，微处理器具有与程序存储器和数据存储器耦合的中央处理单元，被配置为选择多达64个存储体中的一个的存储体选择寄存器以及可操作来寻址高达16KB数据存储器的间接寻址寄存器。 CPU被配置为执行具有两个指令字并被配置为仅访问数据存储器的较低4KB的第一移动指令和具有三个指令字并被配置为访问整个数据存储器的第二移动指令。

公开(公告)号：WO2013052718A1

公开(公告)日：2013-04-11

申请号：PCT/US2012/058832

申请日：2012-10-05

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： LUNDSTRUM, Zeke ,  CURTIS, Keith ,  DAVISON, Burke ,  STEEDMAN, Sean ,  LEFAOU, Yann

IPC: H03M1/12

CPC classification number: H03M1/1245

Abstract: An ADC module includes an analog to digital converter coupled with an analog bus, wherein the an analog to digital converter comprises a main sample and hold capacitor; and a plurality of additional sample and hold capacitances which can be programmably coupled in parallel with said main sample and hold capacitance.

Abstract translation: ADC模块包括与模拟总线耦合的模数转换器，其中模数转换器包括主采样和保持电容器; 以及可以与所述主采样和保持电容并行编程地耦合的多个附加采样和保持电容。

公开(公告)号：WO2010011651A1

公开(公告)日：2010-01-28

申请号：PCT/US2009/051251

申请日：2009-07-21

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  ZDENEK, Jerrold, S. ,  JULICHER, Joseph ,  DELPORT, Vivien ,  STEEDMAN, Sean

Inventor： ZDENEK, Jerrold, S. ,  JULICHER, Joseph ,  DELPORT, Vivien ,  STEEDMAN, Sean

IPC: G06F12/06 ,  G06F9/30

CPC classification number: G06F9/3012 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/342 ,  G06F12/06

Abstract: A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.

Abstract translation: 处理器设备具有具有线性地址空间的数据存储器，数据存储器可通过多个存储体访问。 存储体的至少一个子集被组织成使得子集的每个存储体具有至少第一和第二存储区，其中由多个连续存储体的第二存储区形成连续的存储块。 提供地址调整单元，当使用预定义的地址范围时，将预定义地址范围内的地址翻译成访问所述第二存储区域，使得通过地址，多个第二存储区域形成连续的线性存储器块。

公开(公告)号：WO2009073542A1

公开(公告)日：2009-06-11

申请号：PCT/US2008/084939

申请日：2008-11-26

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

Inventor： JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

IPC: G06F9/46

CPC classification number: G06F9/461

Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

Abstract translation: 微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以是存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时 从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

公开(公告)号：WO2008137718A1

公开(公告)日：2008-11-13

申请号：PCT/US2008/062470

申请日：2008-05-02

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  STEEDMAN, Sean ,  LOURENS, Ruan ,  HULL, Richard

Inventor： STEEDMAN, Sean ,  LOURENS, Ruan ,  HULL, Richard

IPC: H03K17/22 ,  G06F1/28 ,  G06F1/32 ,  G01R19/165 ,  H03K17/00

CPC classification number: H03K17/22 ,  G01R19/16552 ,  G06F1/24 ,  G06F1/30 ,  H03K2217/0036

Abstract: A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

Abstract translation: 具有可编程功率和响应时间特性的欠压复位电路。 这些特性可以通过n位宽的总线编程，用于2n种不同的特性，从非常低的功耗和较慢的响应时间到非常快的响应时间和更高的功耗。 可以使用串行一线总线来代替n位宽的总线。

公开(公告)号：WO2018085616A1

公开(公告)日：2018-05-11

申请号：PCT/US2017/059848

申请日：2017-11-03

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： STEEDMAN, Sean ,  KILZER, Kevin ,  SENAPATI, Ashish ,  MILKS, Justin ,  PULIPAKA, Prashanth

IPC: G06F13/34

CPC classification number: G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/34 ,  G06F13/4068

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

Abstract translation: 公开了一种用于准许在多个仲裁器客户端和中央处理单元之间访问系统总线的可编程系统仲裁器。 可编程系统仲裁器可以包括一个或多个中断优先级寄存器，所述一个或多个中断优先级寄存器中的每一个与中断类型相关联; 以及系统仲裁逻辑，可操作用于至少基于对编程的优先级顺序的分析来仲裁对所述多个仲裁器客户端和所述CPU之间的所述系统总线的访问，所编程的优先级顺序包括所述多个仲裁器客户端中的每一个的优先级顺序， 中央处理单元的多个操作模式中的每一个，以及一个或多个中断类型中的每一个。

公开(公告)号：WO2014138528A1

公开(公告)日：2014-09-12

申请号：PCT/US2014/021543

申请日：2014-03-07

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： STEEDMAN, Sean ,  DUVENHAGE, Fanie

IPC: H03K19/0185 ,  G06F1/32

CPC classification number: H03K3/356104 ,  G06F1/3243 ,  H03K19/018557 ,  H03K19/018585 ,  Y02D10/152

Abstract: An integrated circuit including a processor configured to operate off a supply voltage being applied at one of a plurality of external pins; and internal input/output circuitry configured to select between the supply voltage and at least one other supply voltage being applied at another of the plurality of external pins.

Abstract translation: 一种集成电路，包括：处理器，被配置为操作断开施加在多个外部引脚中的一个上的电源电压; 以及内部输入/输出电路，其被配置为在所述电源电压和在所述多个外部引脚中的另一个上施加的至少一个其它电源电压之间进行选择。

公开(公告)号：WO2013142450A1

公开(公告)日：2013-09-26

申请号：PCT/US2013/032876

申请日：2013-03-19

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： LUNDSTRUM, Zeke ,  DUVENHAGE, Fanie ,  STEEDMAN, Sean ,  KILZER, Kevin, Lee ,  JULICHER, Joseph

IPC: G06F9/30

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30138

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract translation: 微处理器或微控制器设备可以具有中央处理单元（CPU），与CPU耦合的数据存储器，其中数据存储器被分成多个存储体，其中存储体选择寄存器确定当前与 中央处理器。 此外，提供了第一组和第二组特殊功能寄存器，其中在上下文切换发生时，第一组或第二组特殊功能寄存器被选择为用于CPU和相应的另一组特殊功能寄存器的活动上下文寄存器 被选择为非活动上下文寄存器，其中活动上下文寄存器的至少一些寄存器被存储器映射到数据存储器的多于两个存储体，并且其中非活动上下文寄存器的所有寄存器被存储器映射到至少一个存储器位置 在数据存储器内。