公开(公告)号：WO2016153965A1

公开(公告)日：2016-09-29

申请号：PCT/US2016/023033

申请日：2016-03-18

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： PESAVENTO, Rodney ,  SIMMONS, Michael

IPC: G11C17/18 ,  G11C7/10

CPC classification number: G11C17/16 ,  G11C7/1006 ,  G11C17/18 ,  G11C29/76 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: Systems and method for controlling the programming of a one-time programmable (OTP) memory are disclosed. The systems and methods include an OTP memory array comprising an array organized in lines of n+1 bit, wherein n is an integer number designating a word size of the OTP memory, wherein the additional bit indicates whether a memory line is stored in an inverted or non-inverted fashion, encoding logic configured determine whether a word is to be stored inverted or non-inverted, and decoding logic configured to decode a stored word and controlled by the additional bit indicating whether a word has been stored inverted or non-inverted.

Abstract translation: 公开了一种用于控制一次性可编程（OTP）存储器的编程的系统和方法。 该系统和方法包括一个OTP存储器阵列，其包括以n + 1位行的形式组织的阵列，其中n是指定OTP存储器的字大小的整数，其中附加位指示存储器线是否以倒置 或非反转方式，配置的编码逻辑确定字是否被反转或非反相存储，以及解码逻辑，其被配置为对所存储的字进行解码并由附加位控制，指示字是否已被反转或非反相存储 。

公开(公告)号：WO2016077189A1

公开(公告)日：2016-05-19

申请号：PCT/US2015/059661

申请日：2015-11-09

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CASADY, James ,  PESAVENTO, Rodney ,  PAVLOV, Sergey

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/1673 ,  G06F13/385 ,  G06F13/4282 ,  G06F13/4291

Abstract: A serial peripheral interface is configurable to operate in a I2S transmission mode. The interface has a transmission unit connected with external pins for data, bit clock, and left/right clock signal, a first-in-first-out (FIFO) buffer with a plurality of memory lines, and a control unit operable to read data portions from two memory lines, to assemble them into a transmission word, and to forward the assembled transmission word to the transmission unit, wherein the transmission unit is configured to serially transmit the assembled transmission word through the external data pin.

Abstract translation: 串行外设接口可配置为在I2S传输模式下工作。 接口具有与外部引脚连接的传输单元，用于数据，位时钟和左/右时钟信号，具有多条存储器线的先进先出（FIFO）缓冲器，以及可操作以读取数据的控制单元 来自两个存储器线的部分，以将它们组装成传输字，并将组装的传输字转发到传输单元，其中传输单元被配置为通过外部数据引脚串行传输组装的传输字。

公开(公告)号：WO2014160375A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/026424

申请日：2014-03-13

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： SAMUEL, Roshan ,  PESAVENTO, Rodney ,  WOJEWODA, Igor

IPC: G06F9/44

CPC classification number: G06F9/441 ,  G06F9/4408

Abstract: A multi-boot device capable of booting from a plurality of boot devices, each storing a boot image. The multi-boot device determines which boot device to load based on sequence numbers assigned to each of the boot devices. Some embodiments will make this determination using only hardware operations. The multi-boot device compares the sequence numbers of the available boot devices in order to determine the boot image to be loaded. The address of the selected boot image is then mapped to the device's default boot vector. The remaining images are likewise mapped to a secondary boot memory. The device then boots from the default boot vector. The user can change the boot device to be loaded by modifying one or more of the boot sequence numbers. The boot images can be updated without resetting the device by switching execution to and from boot images in the secondary boot memory.

Abstract translation: 一种能够从多个引导设备引导的多引导设备，每个引导设备存储引导映像。 多引导设备基于分配给每个引导设备的序列号确定要加载的引导设备。 一些实施例将仅使用硬件操作进行该确定。 多引导设备比较可用引导设备的序列号，以确定要加载的引导映像。 然后将所选引导映像的地址映射到设备的默认引导向量。 其余图像同样映射到辅助引导存储器。 然后，设备将从默认启动向量启动。 用户可以通过修改一个或多个引导序列号来更改要加载的引导设备。 可以更新引导映像，而不需要通过切换第二引导存储器中的引导映像的执行来重置设备。

公开(公告)号：WO2010056727A1

公开(公告)日：2010-05-20

申请号：PCT/US2009/063998

申请日：2009-11-11

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  LAHTI, Gregg ,  PESAVENTO, Rodney ,  TRIECE, Joseph, W. ,  SESSIONS, D., C.

Inventor： LAHTI, Gregg ,  PESAVENTO, Rodney ,  TRIECE, Joseph, W. ,  SESSIONS, D., C.

IPC: G06F13/12 ,  G06F13/28

CPC classification number: G06F13/124 ,  G06F13/28 ,  Y02D10/14

Abstract: A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

Abstract translation: 微控制器或集成系统具有总线，与总线耦合的多个外围设备，非易失性存储器和与非易失性存储器耦合的状态机，并且可操作以通过读取初始化信息来初始化外围设备 从非易失性存储器写入外围设备。