公开(公告)号：WO2014159388A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/023349

申请日：2014-03-11

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： YUENYONGSGOOL, Yong ,  WOJEWODA, Igor ,  ALKHIMENOK, Anton ,  OTTEN, Kim ,  PAVLOV, Sergey

IPC: G06F1/04 ,  G06F1/10 ,  H03H17/06

CPC classification number: G06F1/04 ,  G06F1/10 ,  H03H17/0642

Abstract: A processor according to embodiments comprises an on-board sample rate converter for converting a source audio signal that is sampled at a first sampling rate to an output audio signal that is sampled at a second sampling rate. The sample rate converter utilizes a master clock signal in converting the audio signal. The sample rate converter selects the master clock signal from available reference clock signals, such as an on-chip system clock or a bus interface clock, and scales the frequency of the selected clock signal to generate the master clock signal with the frequency of the second sampling rate.

Abstract translation: 根据实施例的处理器包括板载采样率转换器，用于将以第一采样率采样的源音频信号转换为以第二采样率采样的输出音频信号。 采样率转换器利用主时钟信号来转换音频信号。 采样率转换器从可用的参考时钟信号（例如片上系统时钟或总线接口时钟）中选择主时钟信号，并且缩放所选时钟信号的频率，以产生具有第二频率的主时钟信号 采样率。

公开(公告)号：WO2013048726A1

公开(公告)日：2013-04-04

申请号：PCT/US2012/054733

申请日：2012-09-12

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  BOWLING, Stephen ,  WOJEWODA, Igor

Inventor： BOWLING, Stephen ,  WOJEWODA, Igor

IPC: G06F1/14 ,  G06F1/32

CPC classification number: G06F1/14 ,  G06F1/3243 ,  G06F1/3287 ,  G06F15/7814 ,  G06F15/7853 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: - a timer being clocked by an independent clock signal; - a comparator coupled with a timer register of said timer and having an output generating an output signal; - an event register coupled with said comparator; - a delta time register; and - an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.

Abstract translation: 微控制器具有中央处理单元（CPU），多个外围设备和可编程调度器单元，其具有： - 由独立时钟信号计时的定时器; - 与所述定时器的定时器寄存器耦合并具有产生输出信号的输出的比较器; - 与所述比较器耦合的事件寄存器; - 增量时间寄存器 以及 - 由比较器的输出信号和第一和第二输入和输出控制的算术逻辑单元，其中第一输入与定时器寄存器或事件寄存器耦合，第二输入与增量时间寄存器耦合， 输出与事件寄存器耦合。

公开(公告)号：WO2019084224A1

公开(公告)日：2019-05-02

申请号：PCT/US2018/057437

申请日：2018-10-25

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： YUENYONGSGOOL, Yong ,  BOWLING, Stephen ,  VAN EEDEN, Cobus ,  WOJEWODA, Igor ,  RAJ, Naveen

IPC: G06F13/28

Abstract: A memory management circuit includes a direct memory access (DMA) channel. The DMA channel incudes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

公开(公告)号：WO2019079083A3

公开(公告)日：2019-04-25

申请号：PCT/US2018/055151

申请日：2018-10-10

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： BOWLING, Stephen ,  YUENYONGSGOOL, Yong ,  WOJEWODA, Igor ,  PHOENIX, Timothy ,  FERNANDES, Dereck ,  BRADLEY, Steve ,  BALU, Manivannan

IPC: G11C29/12 ,  G11C29/14 ,  G06F15/80 ,  G11C29/48 ,  G11C29/26

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

公开(公告)号：WO2016061429A1

公开(公告)日：2016-04-21

申请号：PCT/US2015/055874

申请日：2015-10-16

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： BARTLING, James E. ,  WOJEWODA, Igor ,  KILZER, Kevin

IPC: H03M1/12 ,  H03K17/96 ,  H03M1/50

CPC classification number: H03M1/12 ,  G06F1/32 ,  H03K17/9622 ,  H03K2217/960725 ,  H03M1/00 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/50

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Abstract translation: 微编码序列器控制独立于中央处理单元（CPU）的复杂转换序列。 微编码提供了轻松添加新的流程步骤和/或更新现有的流程步骤。 与诸如模数转换器（ADC）或充电时间测量单元（CTMU）之类的模 - 数转换模块和数字处理电路组合的这种可编程序定序器可被配置为独立于CPU 与微编码序列器结合使用。 因此，当CPU和其他高功率模块处于低功耗睡眠模式时，能够以低功率模式提供自给自足的操作。 这样的外设可以执行数据收集和处理，然后在需要时唤醒CPU，从而节省电力。 此外，该外设不需要CPU处理，因此需要CPU控制的时间关键应用程序可以更有效地运行，同时减少运营负担。

公开(公告)号：WO2008130909A1

公开(公告)日：2008-10-30

申请号：PCT/US2008/060314

申请日：2008-04-15

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  WOJEWODA, Igor ,  KAVAIYA, Gaurang ,  PHOENIX, Tim

Inventor： WOJEWODA, Igor ,  KAVAIYA, Gaurang ,  PHOENIX, Tim

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1028 ,  H03M1/1225

Abstract: A mixed signal device having an analog-to-digital converter (ADC) with offset and gain calibration using internal voltage references whereby the digital processor calibrates out offset and gain errors in the analog-to-digital converter by adjusting the analog input amplifier gain and offset or with software compensating the digital representations of the voltages measured. Two different known voltage values are used in determining the offset and gain adjustments needed to calibrate the ADC against the two know voltage values. The mixed signal device may further comprise a Bandgap voltage reference having an accurate known voltage value. Wherein the Bandgap voltage reference may be used for further offset and gain calibration of the ADC to produce substantially absolute voltage values.

Abstract translation: 一种混合信号装置，其具有使用内部电压基准的具有偏移和增益校准的模数转换器（ADC），由此数字处理器通过调整模拟输入放大器增益来校准模拟 - 数字转换器中的失调和增益误差， 补偿或补偿测量电压的数字表示。 使用两种不同的已知电压值来确定根据两个已知电压值校准ADC所需的偏移和增益调整。 混合信号装置还可以包括具有精确的已知电压值的带隙电压基准。 其中带隙参考电压可用于ADC的进一步偏移和增益校准，以产生基本上绝对的电压值。

公开(公告)号：WO2005043385A1

公开(公告)日：2005-05-12

申请号：PCT/US2004/034730

申请日：2004-10-20

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  WOJEWODA, Igor ,  TRIECE, Joseph, W.

Inventor： WOJEWODA, Igor ,  TRIECE, Joseph, W.

IPC: G06F9/318

CPC classification number: G06F9/30145 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3822

Abstract: A method, system and apparatus are provided for alternating instruction sets in central processing units. A microcontroller is provided with a configuration mechanism, such as a fuse that, depending upon the setting, determines which of multiple instruction sets (or multiple parts of a single instruction set) can be processed by the central processing unit. By changing the fuse setting the characteristics of the central processing unit, and thus the microcontroller as a whole, can be changed.

Abstract translation: 提供了一种用于在中央处理单元中交替指令集的方法，系统和装置。 微控制器具有配置机构，例如根据该设置确定中央处理单元可以处理多个指令集（或单个指令集的多个部分）哪一个）的保险丝。 通过改变熔丝设置，可以改变中央处理单元的特性，从而整个微控制器的特性。

公开(公告)号：WO2016149078A2

公开(公告)日：2016-09-22

申请号：PCT/US2016/021962

申请日：2016-03-11

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： KRIS, Bryan ,  WOJEWODA, Igor ,  CATHERWOOD, Mike ,  FALL, Brian ,  TOLLEFSON, Jason ,  WILKIE, Calum ,  MICKEY, Dave ,  SPOHRER, Thomas ,  DUMAIS, Alex

IPC: G06F15/78 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data bus width of the first and second microcontroller.

Abstract translation: 微控制器装置具有外壳，该外壳具有多个具有多个输入/输出引脚的外部引脚，具有第一中央处理单元（CPU）的第一微控制器，与第一系统总线耦合的第一系统总线 CPU，与第一系统总线耦合的第一存储器以及与第一系统总线耦合的第一多个外围设备，具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，第二存储器 与所述第二系统总线耦合，以及与所述第二系统总线耦合的第二多个外围设备，以及可控制的所述垫所有权多路复用器单元以将所述输入/输出引脚的控制分配给所述第一微控制器或所述第二微控制器，其中所述 外部引脚的数量少于第一个和第二个微控制器的数据总线宽度的总和。

公开(公告)号：WO2014159849A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/025329

申请日：2014-03-13

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： CATHERWOOD, Michael, I. ,  IVEY, Brant ,  WOJEWODA, Igor ,  MICKEY, David ,  KANELLOPOULOS, Joseph

IPC: G06F9/445 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F8/656 ,  G06F9/441

Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

Abstract translation: 公开了一种具有双引导功能的中央处理单元，包括指令存储器，进一步包括被配置为可单独编程的第一和第二存储器区域，其中第一和第二存储器区域可被分配给执行指令的有效存储器， 不活动内存。 用于中央处理单元的指令集包括允许执行从活动存储器区域到非活动存储器区域的交换的专用指令，其中通过在活动存储器中执行专用指令，然后执行程序流程改变来执行交换 指令在活动存储器中，因此非活动存储器变为新的活动存储器，并且活动存储器变为新的非活动存储器，并且在新的活动存储器中继续执行指令。

公开(公告)号：WO2014149583A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/019737

申请日：2014-03-01

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： SIMMONS, Michael ,  WOJEWODA, Igor ,  SAMUEL, Roshan

IPC: G06F9/445 ,  G06F9/44

CPC classification number: G06F1/24 ,  G06F8/656 ,  G06F9/4401 ,  G06F9/4406 ,  G06F9/4411 ,  G06F9/44505

Abstract: A method for hot swapping an operating system kernel in a system, wherein the system comprises a central processing unit, one or more system components and a program memory including an old kernel and a new kernel, the method comprising: - configuring, by the old kernel, the system to boot from the new kernel by branching into a suitable entry point in the new kernel; - identifying, by the new kernel, one or more system components which require a reinitialization or reset; - further executing the new kernel in order to reinitialize or reset the one or more system components.

Abstract translation: 一种用于热交换系统中的操作系统内核的方法，其中所述系统包括中央处理单元，一个或多个系统组件以及包括旧内核和新内核的程序存储器，所述方法包括： - 由旧的 内核，系统通过分支到新内核中的合适入口点从新内核引导; - 由新内核识别需要重新初始化或重置的一个或多个系统组件; - 进一步执行新内核以重新初始化或重置一个或多个系统组件。