公开(公告)号：WO2014186529A1

公开(公告)日：2014-11-20

申请号：PCT/US2014/038110

申请日：2014-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： RAMASWAMY, D.V. Nirmal ,  JOHNSON, Adam D.

IPC: H01L29/78 ,  H01L21/335

CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

Abstract: An apparatus comprises field effect transistor (FET) structures stacked horizontally and vertically in a three dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

Abstract translation: 一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。 在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。 另一种装置包括多个位线和字线。 每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻栅极共享以形成多个FeFET。 操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元。