公开(公告)号：WO2016190880A1

公开(公告)日：2016-12-01

申请号：PCT/US2015/032943

申请日：2015-05-28

Applicant: INTEL CORPORATION

Inventor： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  YOUNG, Ian A.

IPC: G11C11/15

CPC classification number: G11C14/0072 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C14/0027 ,  H01L27/11502

Abstract: Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.

Abstract translation: 描述了一种装置，包括：由写入字线（WWL）控制的第一存取晶体管; 由读取字线（RWL）控制的第二存取晶体管; 以及耦合到所述第一和第二存取晶体管的铁电单元，其中所述铁电单元可经由所述WWL可编程并经由所述RWL可读。 描述了一种方法，其包括：驱动连接到第一存取晶体管的栅极端子的WWL，以使第一存取晶体管导通; 以及驱动耦合到所述第一存取晶体管的源极/漏极端子的WBL，所述驱动WBL在所述第一存取晶体管导通时对与所述第一存取晶体管耦合的存储节点进行充电或放电，其中所述铁电单元耦合到 存储节点并根据充电或放电存储节点进行编程。

公开(公告)号：WO2016048653A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/049004

申请日：2015-09-08

Applicant: RADIANT TECHNOLOGIES, INC

Inventor： EVANS, JR., Joseph, T.

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2253 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract translation: 公开了一种存储单元和由该存储单元构成的存储器。 根据本发明的存储器包括铁电电容器，电荷源和读取电路。 电荷源接收要存储在铁电电容器中的数据值。 电荷源将数据值转换为存储在铁电电容器中的剩余电荷，并使残留电荷存储在铁电体电容器中。 读取电路确定存储在铁电体电容器中的电荷。 数据值具有三个不同的可能状态，并且所确定的电荷具有多于三个确定的值。 存储器还包括使铁电电容器进入预定的已知参考偏振状态的复位电路。

公开(公告)号：WO2016028356A1

公开(公告)日：2016-02-25

申请号：PCT/US2015/033983

申请日：2015-06-03

Applicant: SABIC GLOBAL TECHOLOGIES B.V ,  PARK, Ji, Hoon ,  ALSHAREEF, Husam, N. ,  KHAN, Mohd, A. ,  ODEN, Ihab, N.

Inventor： PARK, Ji, Hoon ,  ALSHAREEF, Husam, N. ,  KHAN, Mohd, A. ,  ODEN, Ihab, N.

IPC: H01L43/08 ,  G11C11/15

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2277 ,  G11C11/5657 ,  H01L27/11509 ,  H01L27/20

Abstract: Ferroelectric components, such as the ferroelectric field effect transistors (FeFETs), ferroelectric capacitors and ferroelectric diodes described above may be operated as multi-level memory cells as described by the present invention. Storing multiple bits of information in each multi-level memory cell may be performed by a controller coupled to an array of the ferroelectric components configured as ferroelectric memory cells. The controller may execute the steps of receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.

Abstract translation: 诸如铁电场效应晶体管（FeFET），铁电电容器和铁电二极管的铁电元件可以作为如本发明所述的多电平存储器单元来操作。 在每个多级存储器单元中存储多个位的信息可以由耦合到被配置为铁电存储单元的铁电元件阵列的控制器来执行。 控制器可以执行以下步骤：接收用于写入到包括铁电层的多层存储单元的位模式; 至少部分地基于所接收的位模式，选择用于将写入脉冲施加到存储器单元的脉冲持续时间; 以及向具有所选择的脉冲持续时间的存储单元施加至少一个写入脉冲，其中所述至少一个写入脉冲在所述铁电层内产生代表所接收的位模式的剩余极化。

公开(公告)号：WO2015112609A1

公开(公告)日：2015-07-30

申请号：PCT/US2015/012260

申请日：2015-01-21

Applicant: RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T.

Inventor： EVANS, Joseph, T.

IPC: H03K21/08

CPC classification number: H03K21/08 ,  G11C11/221 ,  H03K23/766

Abstract: A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.

Abstract translation: 公开了可以包括多个计数级的计数器。 每个计数级包括由第一和第二极化状态表征的铁电电容器，可变阻抗元件，复位和计数端口以及检测器。 可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗，铁电电容器连接在控制端子和第一开关端子之间。 耦合到控制端子的复位信号使铁电电容器在第一偏振状态下被极化。 计数端口被配置为接收待计数的脉冲，计数端口通过导电负载连接到第一开关端子。 如果计数端口正在接收到其中一个脉冲，则第一端子上的电位超过阈值时，检测器产生计数完成信号。

公开(公告)号：WO2014186529A1

公开(公告)日：2014-11-20

申请号：PCT/US2014/038110

申请日：2014-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： RAMASWAMY, D.V. Nirmal ,  JOHNSON, Adam D.

IPC: H01L29/78 ,  H01L21/335

CPC classification number: H01L27/11597 ,  G11C11/22 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/78391

Abstract: An apparatus comprises field effect transistor (FET) structures stacked horizontally and vertically in a three dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.

Abstract translation: 一种装置包括在三维存储阵列结构中水平和垂直堆叠的场效应晶体管（FET）结构，在多个FET结构之间垂直和水平间隔延伸的栅极和分离FET结构和栅极的铁电材料。 在FET结构，栅极和铁电体材料的交叉处形成单个铁电FET（FeFET）。 另一种装置包括多个位线和字线。 每个位线具有与铁电材料耦合的至少两个边，使得每个位线由相邻栅极共享以形成多个FeFET。 操作存储器阵列的方法包括将电压的组合施加到多个字线和数字线以用于多个FeFET存储器单元的期望操作，至少一个数字线具有可由相邻门访问的多个FeFET存储器单元。

公开(公告)号：WO2013184797A1

公开(公告)日：2013-12-12

申请号：PCT/US2013/044308

申请日：2013-06-05

Applicant: SAUDI BASIC INDUSTRIES CORPORATION ,  ALSHAREEF, Husam N.

Inventor： ALSHAREEF, Husam N. ,  UNNAT, Bhansali ,  KHAN, Mohd Adnan ,  SALEH, Moussa M. ,  ODEH, Ihab N.

IPC: H01L49/02 ,  C08G61/12 ,  C08L25/18 ,  H01B1/12 ,  H01G4/008 ,  H01G4/14 ,  H01L23/532 ,  H01L51/00 ,  G11C11/22 ,  H01L27/10

CPC classification number: H01L51/102 ,  B82Y10/00 ,  C08G61/126 ,  C08G2261/1424 ,  C08G2261/3223 ,  C08G2261/51 ,  C08G2261/794 ,  C08G2261/92 ,  C08G2261/95 ,  C08L25/18 ,  C08L65/00 ,  G11C11/221 ,  H01B1/127 ,  H01B1/128 ,  H01G4/18 ,  H01G4/206 ,  H01G7/06 ,  H01L27/101 ,  H01L28/55 ,  H01L28/60 ,  H01L51/0001 ,  H01L51/0037 ,  H01L51/0591

Abstract: A doped electroconductive organic polymer is used for forming the electrode of a ferroelectric device or an interconnect. An exemplary ferroelectric device is a ferrelectric capacitor comprising: a substrate (101); a first electrode (106) disposed on the substrate; a ferroelectric layer (112) disposed on and in contact with the first electrode; and a second electrode (116) disposed on and in contact with the ferroelectric layer, wherein at least one of the first electrode and the second electrode is an organic electrode comprising a doped electroconductive organic polymer, for example DMSO-doped PEDOT-PSS.

Abstract translation: 掺杂的导电有机聚合物用于形成铁电体器件或互连件的电极。 示例性的铁电体装置是一种电介质电容器，包括：基板（101）; 设置在所述基板上的第一电极（106） 设置在第一电极上并与第一电极接触的铁电层（112）; 以及设置在铁电层上并与铁电层接触的第二电极（116），其中第一电极和第二电极中的至少一个是包括掺杂的导电有机聚合物（例如DMSO掺杂的PEDOT-PSS）的有机电极。

公开(公告)号：WO2012153855A8

公开(公告)日：2013-01-17

申请号：PCT/JP2012062232

申请日：2012-05-11

Applicant: AJINOMOTO KK ,  OHASHI SATORU ,  UEMURA SEI ,  KITAZAWA MANABU ,  KAMATA TOSHIHIDE

Inventor： OHASHI SATORU ,  UEMURA SEI ,  KITAZAWA MANABU ,  KAMATA TOSHIHIDE

IPC: H01L21/8246 ,  H01L21/336 ,  H01L27/105 ,  H01L27/28 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L51/05 ,  H01L51/30

CPC classification number: C08G63/685 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/221 ,  H01L29/78391 ,  H01L51/0002 ,  H01L51/0003 ,  H01L51/0512 ,  H01L51/052 ,  H01L51/0591

Abstract: Provided are a poly a-amino acid having good film-producing capability, and a ferromagnetic memory element having excellent moldability and workability and further, excellent operating stability when exposed to high temperatures. The ferromagnetic memory element comprises a poly a-amino acid that is a copolymer formed from glutamic acid-?-ester units represented by formula (I) (I) (where R1 is an optionally substituted C1-8 alkyl group or benzyl group optionally substituted by a halogen atom, alkoxy group or nitro group) and glutamic acid-?-ester units represented by formula (II) (II) (where R2 is not the same as R1 and is an unsubstituted C3-16 alkyl group or C1-6 alkyl group wherein a portion or all of the hydrogen atoms are optionally substituted by halogen atoms, C3-12 acyclic hydrocarbon groups, C1-6 alkoxy groups, cyano groups, phenyl groups (where a portion or all of the hydrogen atoms are optionally substituted by halogen atoms or alkoxy groups), phenyl alkoxy groups (where a portion or all of the hydrogen atoms are optionally substituted by halogen atoms or alkoxy groups), or phenyl alkyl carbamate groups (where a portion or all of the hydrogen atoms are optionally substituted by halogen atoms or alkoxy groups)) and has a ratio of units represented by formula (I) and units represented by formula (II) ((I)/(II)) that is between 10/90 and 90/10 by molar ratio.

Abstract translation: 提供了具有良好的膜生产能力的聚α-氨基酸和具有优异的成型性和加工性的铁磁记忆元件，并且当暴露于高温时具有优异的操作稳定性。 铁磁存储元件包括由式（I）（I）表示的谷氨酸-β-酯单元形成的共聚物的聚α-氨基酸（其中R 1是任选取代的C 1-8烷基或任选取代的苄基） 通过卤素原子，烷氧基或硝基）和由式（II）（II）表示的谷氨酸-β-酯单元（其中R 2不与R 1相同，为未取代的C 3-6-16烷基或C 1-6 烷基，其中一部分或全部氢原子任选地被卤素原子取代，C 3-12无环烃基，C 1-6烷氧基，氰基，苯基（其中部分或全部氢原子任选地被 卤素原子或烷氧基），苯基烷氧基（其中一部分或全部氢原子任选被卤素原子或烷氧基取代）或苯基烷基氨基甲酸酯基（其中部分或全部氢原子任选被 卤素原子或烷氧基 y）），并且具有由式（I）表示的单元与式（II）（（I）/（II））表示的单元的摩尔比为10/90至90/10的比例。

公开(公告)号：WO2013002601A2

公开(公告)日：2013-01-03

申请号：PCT/KR2012005186

申请日：2012-06-29

Applicant: KWANGJU INST SCI & TECH ,  LEE BYOUNG HUN ,  HWANG HYEON JUN

Inventor： LEE BYOUNG HUN ,  HWANG HYEON JUN

CPC classification number: G11C11/221 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/788

Abstract: Provided are a memory device using graphene and a method for manufacturing same. The memory device using graphene comprises: at least one programming electrode arranged so as to intersect with a graphene layer; and a ferroelectric layer interposed between the graphene layer and the programming electrode. Thus, the memory device may have non-volatile properties using a difference in resistances of the graphene layer due to the polarity of a polling voltage applied through the at least one programming electrode. Further, two or more programming electrodes are arranged, and polling voltages of the same polarity or different polarities are applied to each programming electrode, thereby achieving multi-bits. In addition, the method for manufacturing the memory device using graphene involves forming only one ferroelectric layer capable of maintaining polarization through polling, thus enabling an electric field to be continuously applied to the graphene layer contacting the ferroelectric layer.

Abstract translation: 提供了使用石墨烯的存储器件及其制造方法。 使用石墨烯的存储器件包括：布置成与石墨烯层相交的至少一个编程电极; 以及介于石墨烯层和编程电极之间的铁电层。 因此，由于通过至少一个编程电极施加的轮询电压的极性，存储器件可以具有使用石墨烯层的电阻差异的非易失性特性。 此外，布置两个或更多个编程电极，并且将相同极性或不同极性的轮询电压施加到每个编程电极，从而实现多位。 此外，使用石墨烯制造存储器件的方法包括仅形成能够通过轮询维持极化的一个铁电层，从而能够将电场连续施加到与铁电层接触的石墨烯层。

公开(公告)号：WO2017151192A1

公开(公告)日：2017-09-08

申请号：PCT/US2016/060467

申请日：2016-11-04

Applicant: CYPRESS SEMICONDUCTOR CORPORATION

Inventor： CHU, Fan ,  SUN, Shan ,  DEVILBISS, Alan ,  DAVENPORT, Thomas

IPC: G11C11/22 ,  H01L27/115

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2253 ,  H01L27/11507 ,  H01L27/11509

Abstract: An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in which the second signal component is temperature dependent.

Abstract translation: 一种包括参考产生电路的设备，所述参考产生电路经配置以产​​生用于非易失性存储器（NVM）装置的参考信号，所述参考产生电路包含第一电路，所述第一电路包括至少一个金属氧化物半导体 电容器，第一电路产生参考信号的第一信号分量，以及第二电路包括至少一个铁电电容器，第二电路产生参考信号的第二信号分量，其中第二信号分量取决于温度。 / p>

公开(公告)号：WO2017048229A1

公开(公告)日：2017-03-23

申请号：PCT/US2015/050056

申请日：2015-09-14

Applicant: INTEL CORPORATION

Inventor： MANIPATRUNI, Sasikanth ,  NIKONOV, Dmitri E. ,  CHAUDHRY, Anurag ,  YOUNG, Ian A.

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C11/221 ,  H01L27/228 ,  H01L43/00

Abstract: Described is an apparatus which comprises: a first transistor; a second transistor having a first terminal coupled to a first terminal of the first transistor; a first conductor coupled to a second terminal of the second transistor; a magnetoelectric (ME) layer coupled to the first conductor; and a ferromagnetic (FM) layer coupled to the ME layer and to a second terminal of the first transistor.

Abstract translation: 描述了一种装置，包括：第一晶体管; 第二晶体管，其具有耦合到所述第一晶体管的第一端子的第一端子; 耦合到所述第二晶体管的第二端子的第一导体; 耦合到所述第一导体的磁电（ME）层; 以及耦合到ME层和第一晶体管的第二端子的铁磁（FM）层。