公开(公告)号：WO2018044454A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/044633

申请日：2017-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MATHEW, Suraj, J. ,  SINGANAMALLA, Raghunath ,  AHMED, Fawad ,  BROWN, Kris, K. ,  NAIR, Vinay ,  YANG, Gloria ,  SIMSEK-EGE, Fatma, Arzum ,  TRAN, Diem, Thy N.

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract translation: 一些实施例包括具有第一，第二和第三晶体管的存储器单元，其中第二和第三晶体管相对于彼此垂直移位。 存储器单元具有沿第二和第三晶体管延伸的半导体柱，半导体柱包含第二和第三晶体管的沟道区和源极/漏极区。 电容器可以电耦合在第一晶体管的源极/漏极区域和第二晶体管的栅极之间。

公开(公告)号：WO2018044456A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/044638

申请日：2017-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YANG, Gloria ,  MATHEW, Suraj J. ,  SINGANAMALLA, Raghunath ,  NAIR, Vinay ,  DERNER, Scott, J. ,  SHORE, Michael, Amiel ,  KEETH, Brent ,  SIMSEK-EGE, Fatma Arzum ,  TRAN, Diem Thy N.

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract translation: 一些实施例包括具有第一和第二晶体管的存储器单元以及相对于第一和第二晶体管垂直移位的电容器。 电容器具有与第一晶体管的源极/漏极区电耦合的第一节点，与第二晶体管的源极/漏极区电耦合的第二节点以及第一节点和第二节点之间的电容器电介质材料。 一些实施例包括具有相对于彼此垂直移位的第一和第二晶体管的存储器单元，以及在第一和第二晶体管之间的电容器。 电容器具有与第一晶体管的源极/漏极区域电耦合的第一节点，与第二晶体管的源极/漏极区域电耦合的第二节点以及第一节点和第二节点之间的电容器电介质材料。

公开(公告)号：WO2019172970A1

公开(公告)日：2019-09-12

申请号：PCT/US2018/060892

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SHARMA, Pranav, P. ,  NAIR, Vinay ,  SAPRA, Sanjeev

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat- topped peak portion and an adjacent concavity portion.

公开(公告)号：WO2018044453A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/044611

申请日：2017-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MATHEW, Suraj, J. ,  BROWN, Kris, K. ,  SINGANAMALLA, Raghunath ,  NAIR, Vinay ,  AHMED, Fawad ,  SIMSEK-EGE, Fatma, Arzum ,  TRAN, Diem Thy, N.

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

Abstract translation: 一些实施例包括具有由半导体基底支撑的第一晶体管并且在第一晶体管上方具有第二和第三晶体管并且一个在另一个之上垂直堆叠的存储器单元。 一些实施例包括具有第一，第二和第三晶体管的存储器单元。 第三晶体管在第二晶体管之上，第二和第三晶体管在第一晶体管之上。 第一晶体管具有第一和第二源极/漏极区域，第二晶体管具有第三和第四源极/漏极区域，第三晶体管具有第五和第六源极/漏极区域。 读取位线与第六源极/漏极区域耦合。 写入位线与第一源极/漏极区域耦合。 写入字线包括第一晶体管的栅极。 读字线包括第三晶体管的栅极。 电容器与第二源极/漏极区域和第二晶体管的栅极耦合。