公开(公告)号：WO2018044454A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/044633

申请日：2017-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MATHEW, Suraj, J. ,  SINGANAMALLA, Raghunath ,  AHMED, Fawad ,  BROWN, Kris, K. ,  NAIR, Vinay ,  YANG, Gloria ,  SIMSEK-EGE, Fatma, Arzum ,  TRAN, Diem, Thy N.

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Abstract translation: 一些实施例包括具有第一，第二和第三晶体管的存储器单元，其中第二和第三晶体管相对于彼此垂直移位。 存储器单元具有沿第二和第三晶体管延伸的半导体柱，半导体柱包含第二和第三晶体管的沟道区和源极/漏极区。 电容器可以电耦合在第一晶体管的源极/漏极区域和第二晶体管的栅极之间。

公开(公告)号：WO2018044456A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/044638

申请日：2017-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YANG, Gloria ,  MATHEW, Suraj J. ,  SINGANAMALLA, Raghunath ,  NAIR, Vinay ,  DERNER, Scott, J. ,  SHORE, Michael, Amiel ,  KEETH, Brent ,  SIMSEK-EGE, Fatma Arzum ,  TRAN, Diem Thy N.

IPC: H01L27/108

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract translation: 一些实施例包括具有第一和第二晶体管的存储器单元以及相对于第一和第二晶体管垂直移位的电容器。 电容器具有与第一晶体管的源极/漏极区电耦合的第一节点，与第二晶体管的源极/漏极区电耦合的第二节点以及第一节点和第二节点之间的电容器电介质材料。 一些实施例包括具有相对于彼此垂直移位的第一和第二晶体管的存储器单元，以及在第一和第二晶体管之间的电容器。 电容器具有与第一晶体管的源极/漏极区域电耦合的第一节点，与第二晶体管的源极/漏极区域电耦合的第二节点以及第一节点和第二节点之间的电容器电介质材料。