公开(公告)号：WO2020180464A1

公开(公告)日：2020-09-10

申请号：PCT/US2020/017578

申请日：2020-02-11

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent ,  MALIHI, Naveh

IPC分类号： G06F9/455 ,  G06F12/14 ,  G06F21/60

摘要： Apparatuses and methods related to managing regions of memory are described. Managing regions can include verifying whether an access command is authorized to access a particular region of a memory array, which may have some regions that have rules or restrictions governing access (e.g., so-called "protected regions"). The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the region, then a row of the memory array corresponding to the access command may not be activated.

公开(公告)号：WO2020172557A1

公开(公告)日：2020-08-27

申请号：PCT/US2020/019269

申请日：2020-02-21

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent ,  FAY, Owen ,  YOO, Chan H. ,  GREEFF, Roy E. ,  LESLIE, Matthew B.

IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C5/04 ,  H01L23/00 ,  H01L23/498

摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：WO2020139540A1

公开(公告)日：2020-07-02

申请号：PCT/US2019/064906

申请日：2019-12-06

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent ,  MALIHI, Naveh

IPC分类号： G06F12/14 ,  G06F3/06 ,  G06F9/455 ,  G06F13/38 ,  G06F21/62 ,  G06F21/60 ,  G06F21/6245 ,  G06F21/79 ,  G06F2221/2101 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679

摘要： Apparatuses and methods related to tracking unauthorized access commands for memory. Identifying unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then an access count can be incremented to signify the unauthorized access command.

公开(公告)号：WO2009051716A3

公开(公告)日：2009-04-23

申请号：PCT/US2008/011753

申请日：2008-10-15

申请人： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

发明人： KEETH, Brent

IPC分类号： H01L21/66

摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

公开(公告)号：WO2002069341A2

公开(公告)日：2002-09-06

申请号：PCT/US2002/002764

申请日：2002-02-01

申请人： MICRON TECHNOLOGY, INC.

发明人： JANZEN, Jeffery, W. ,  MANNING, Troy, A. ,  MARTIN, Chris, G. ,  KEETH, Brent

IPC分类号： G11C7/22

CPC分类号： G11C7/1066 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409 ,  G11C2207/107 ,  G11C2207/2254 ,  G11C2207/2281

摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

摘要翻译： 通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。 标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。 对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。 然后将延迟应用于在存储器系统的常规操作期间读取事务。

公开(公告)号：WO1998019307A1

公开(公告)日：1998-05-07

申请号：PCT/US1997019580

申请日：1997-10-28

申请人： MICRON TECHNOLOGY, INC.

发明人： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC分类号： G11C07/00

CPC分类号： G11C7/1093 ,  G11C7/1042 ,  G11C7/1078 ,  G11C7/22

摘要： A data bus is described which has integrated circuits, such as memory circuits, coupled thereto. The integrated circuits include an input buffer circuit adapted to receive and latch high speed data transmissions. The input buffer circuit equilibrates a sensing circuit, samples input data, senses the sampled input data, and latches the sensed data during different phases of an input clock cycle. An input buffer circuit is described which has two receiver circuits for receiving data transmissions having higher speed data transmissions.

摘要翻译： 描述了具有集成电路的数据总线，诸如与其耦合的存储器电路。 集成电路包括适于接收和锁存高速数据传输的输入缓冲器电路。 输入缓冲电路平衡感测电路，采样输入数据，感测采样输入数据，并在输入时钟周期的不同阶段锁存感测数据。 描述了一种输入缓冲器电路，其具有用于接收具有较高速度数据传输的数据传输的两个接收器电路。

公开(公告)号：WO1996013003A1

公开(公告)日：1996-05-02

申请号：PCT/US1995013514

申请日：1995-10-19

申请人： MICRON TECHNOLOGY, INC.

发明人： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul, S. ,  KEETH, Brent ,  ONG, Adrian, E.

IPC分类号： G06F11/20

CPC分类号： G11C29/70 ,  G01R31/3004 ,  G06F11/22 ,  G11C11/401 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50 ,  G11C29/83 ,  G11C29/832 ,  G11C29/88 ,  G11C2029/5006

摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

摘要翻译： 集成电路存储器件具有多个子阵列分隔，其可以独立地与集成电路上的剩余电路隔离。 集成电路的子阵列可以独立测试。 如果发现集成电路的子阵列不可操作，则它与集成电路上的剩余电路电隔离，使得其不能干扰剩余电路的正常操作。 以前曾经是灾难性的子阵列中的诸如对地短路的电力的缺陷可以是电隔离的，允许利用剩余的功能子阵列。 通过隔离不起作用元件的集成电路修复消除了以前与集成电路相关的电流消耗和其他性能下降，缺陷通过单独使用冗余元件进行维修。

公开(公告)号：WO2021133826A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/066664

申请日：2020-12-22

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent ,  ROSS, Frank F. ,  MURPHY, Richard C.

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/54 ,  G06F13/1668 ,  G06N3/004 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18

摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

公开(公告)号：WO2020172551A1

公开(公告)日：2020-08-27

申请号：PCT/US2020/019259

申请日：2020-02-21

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent ,  FAY, Owen ,  YOO, Chan H. ,  GREEFF, Roy E. ,  LESLIE, Matthew B.

IPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00

摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：WO2019216987A1

公开(公告)日：2019-11-14

申请号：PCT/US2019/022307

申请日：2019-03-14

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent

IPC分类号： G11C5/04 ,  G11C5/06 ,  G11C7/10

摘要： Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.