公开(公告)号：WO2022266575A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/072635

申请日：2022-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KIM, Kang-Yong ,  LEE, Hyun Yoo ,  SONG, Keun Soo

IPC: G06F1/3234 ,  G06F1/324 ,  G06F1/3287

Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller (110) transitions a memory circuit (124, e.g., of a memory die) from a first power rail (206) to a second power rail (204). The power rail controller (110) then changes a voltage of the first power rail (206) from a first voltage to a second voltage. The power rail controller (110) may also adjust termination impedance (604) or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller (110) then transitions the memory circuit from the second power rail (204) to the first power rail (206) to enable operation of the memory circuit (124) at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：WO2022236338A1

公开(公告)日：2022-11-10

申请号：PCT/US2022/072191

申请日：2022-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SONG, Keun Soo ,  LEE, Hyunyoo ,  KIM, Kang Yong

IPC: G11C7/10 ,  G11C7/22

Abstract: This document describes apparatuses (102) and techniques (700) for termination for single-ended (SE) mode operation of a memory device (114). In various aspects, a termination circuit (118) can terminate an unused signal line of a differential pair (308, 312) to a ground (320) or power rail (504) using a switch element (322) when operating in the SE mode. The termination circuit (118) may also disconnect the unused signal line (312) from a first input of a differential amplifier (202) and connect a reference voltage (504) to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier (202) amplifies an SE signal received using another signal line (308) of the differential pair at a second input of the differential amplifier to provide a clock signal (208) for memory operations. Thus, the termination circuit (118) may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

公开(公告)号：WO2022266576A1

公开(公告)日：2022-12-22

申请号：PCT/US2022/072636

申请日：2022-05-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KIM, Kang-Yong ,  SONG, Keun Soo ,  LEE, Hyun Yoo

IPC: G06F1/324 ,  G06F1/12 ,  G06F1/3234

Abstract: This document describes apparatuses and techniques for write timing compensation. In various aspects, a write timing compensator (112) of a memory controller (108) can apply a delay to data signals transmitted to a memory circuit (124) based on various operating parameters, which may include voltage or latency information. In some cases, the memory controller (108) or memory circuit (124) powers components of write timing compensation circuitry using a dynamic power rail that scales with an operating voltage of the memory circuit. By so doing, the write timing compensator (112) or compensation circuits (402) may improve signal integrity of data signals communicated between the memory controller and the memory circuit at different frequencies and voltages.

公开(公告)号：WO2022198193A1

公开(公告)日：2022-09-22

申请号：PCT/US2022/071134

申请日：2022-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SONG, Keun Soo ,  KIM, Kang-Yong ,  LEE, Hyun Yoo

IPC: G11C29/42 ,  G06F11/10 ,  H03M13/19

Abstract: Described apparatuses and methods provide configurable error correction code, ECC, circuitry (112) and schemes that can utilize a shared ECC engine (408) between two or more memory banks (404) of a memory (110, 208), including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values (412) based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.

公开(公告)号：WO2023034707A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/075403

申请日：2022-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SONG, Keun Soo

IPC: G11C7/10 ,  H03K7/02 ,  G06F3/06

Abstract: This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function (110) of a memory controller (108) may use an unassigned or prohibited PAM signaling state for a set of data lines to indicate data masking to a memory device (116) for a group of data bits. For example, the data mask function (110) may alter a PAM symbol or signal level for at least one data line from a low-voltage state (L) or mid-voltage state (M) state to a high-voltage state (H), resulting in a PAM signaling state for the set of data lines that corresponds data mask indication for the group of data bits. By so doing, the data mask function (110) may indicate data masking for the group of bits without a dedicated data mask signal line, which may enable improved per-line memory bandwidth.

公开(公告)号：WO2022232067A1

公开(公告)日：2022-11-03

申请号：PCT/US2022/026220

申请日：2022-04-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LEE, Hyun Yoo ,  KIM, Kang-Yong ,  DHIR, Sourabh ,  SONG, Keun Soo

IPC: G11C11/4074 ,  G11C5/14

Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.