公开(公告)号：WO2023063568A1

公开(公告)日：2023-04-20

申请号：PCT/KR2022/012869

申请日：2022-08-29

Applicant: 삼성전자주식회사

Inventor： 이명기 ,  변치웅

IPC: G06F1/3234 ,  G06F1/20 ,  G06F1/3225 ,  G06F1/329

Abstract: 메모리 제어 방법 및 상기 방법을 수행하는 전자 장치가 개시된다. 다양한 실시예들에 따른 메모리 제어 방법은 열 관리 유닛(thermal manage unit)에서 프로세서 내부의 온도를 센싱하는 동작, 상기 온도 및 제1 메모리에 인가되는 전압에 기초하여, 상기 제1 메모리의 누설 전류를 예측하는 동작 및 예측된 상기 누설 전류에 기초하여, 상기 제1 메모리의 동작을 제어하는 동작을 포함하고, 상기 프로세서는, 상기 제1 메모리에 접근한 후 상기 제2 메모리에 접근할 수 있다.

公开(公告)号：WO2023034457A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/042267

申请日：2022-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GUAN, Huapeng G. ,  ADI, Frederick ,  ZHU, Jiangli ,  YU, Yipei ,  PASALA, Venkata Naga Lakshman ,  WANG, Wei

IPC: G06F1/3234 ,  G06F1/3225

Abstract: A system for managing power loss can include a number of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices. The processor can save a snapshot of a logical-to-physical (L2P) table to a non-volatile memory device and maintain a journal of updates of the L2P. The processor can, in response to a parameter of journal buffer of a volatile memory device satisfying a threshold criterion, save at least one journal of updates of the L2P table to the non-volatile memory device. It can also retrieve a sequence number from system metadata and save the most recent set of updates of the L2P table to a dedicated area of the non-volatile memory device, where the dedicated area is identified by the sequence number, in response to detecting a power loss event.

公开(公告)号：WO2022271231A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/021350

申请日：2022-03-22

Applicant: INTEL CORPORATION

Inventor： KUMAR, Karthik ,  GUIM BERNAT, Francesc ,  SCHMISSEUR, Mark A

IPC: G06F12/123 ,  G06F12/14 ,  G06F1/3234 ,  G06F12/02 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  G06F12/0607 ,  G06F12/1466 ,  G06F2212/1052

Abstract: The platform data aging for adaptive memory scaling described herein provides technical solutions for technical problems facing power management for electronic device processors. Technical solutions described herein include improved processor power management based on a memory region life-cycle (e.g., short-lived, long-lived, static). In an example, a short-term memory request is allocated to a short-term memory region, and that short-term memory region is powered down upon expiration of the lifetime of all short-term memory requests on the short-term memory region. Multiple memory regions may be scaled down (e.g., shut down) or scaled up based on demands for memory capacity and bandwidth.

公开(公告)号：WO2021141797A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/067261

申请日：2020-12-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CHOI, Baekkyu ,  KINSLEY, Thomas, H. ,  BADRIEH, Fuad

IPC: G11C5/14 ,  G11C5/04 ,  G06F1/3225 ,  G06F1/30

Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.

公开(公告)号：WO2021118711A1

公开(公告)日：2021-06-17

申请号：PCT/US2020/058468

申请日：2020-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： BELL, Debra M. ,  BAGHI, Roya ,  GOVE, Erica M. ,  HOSSEINIMAKAREM, Zahra ,  O'DONNELL, Cheryl M.

IPC: G11C7/04 ,  G06F1/20 ,  G06F1/3225

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

公开(公告)号：WO2020167358A1

公开(公告)日：2020-08-20

申请号：PCT/US2019/063274

申请日：2019-11-26

Applicant: GOOGLE LLC

Inventor： CHAMARTY, Vinod ,  MADAR, Lawrence J., III

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0862 ,  G06F1/3225 ,  G06F1/3234 ,  G06F12/126 ,  H04L29/08

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing a prefetch processing to prepare an ambient computing device to operate in a low-power state without waking a memory device. One of the methods includes performing, by an ambient computing device, a prefetch process that populates a cache with prefetched instructions and data required for the ambient computing device to process inputs to the system while in the low-power state, and entering the low-power state, and processing, by the ambient computing device in the low-power state, inputs to the system using the prefetched instructions and data stored in the cache.

公开(公告)号：WO2023081567A1

公开(公告)日：2023-05-11

申请号：PCT/US2022/077671

申请日：2022-10-06

Applicant: INTEL CORPORATION ,  MATHIYALAGAN, Vijay Anand ,  GUNTHER, Stephen H. ,  KHATAKALLE, Shidlingeshwar ,  CHINNAKKONDA VIDYAPOORNACHARY, Diyanesh Babu

Inventor： MATHIYALAGAN, Vijay Anand ,  GUNTHER, Stephen H. ,  KHATAKALLE, Shidlingeshwar ,  CHINNAKKONDA VIDYAPOORNACHARY, Diyanesh Babu

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/30 ,  G06F1/329 ,  G06F1/3225

Abstract: Systems, apparatuses and methods may provide for operating system (OS) technology that determines an average bandwidth consumption with respect to a memory device, wherein the average bandwidth consumption is dedicated to a previous execution of a thread in a multi-threaded execution environment, stores the average bandwidth consumption, and sends the average bandwidth consumption to a power management unit in response to a subsequent execution of the thread being scheduled. Additionally, logic hardware technology may include a first set of registers to accumulate an average bandwidth consumption for a plurality of threads on a per thread basis with respect to the memory device, wherein the average bandwidth consumption corresponds to previous executions of the plurality of threads. The logic hardware technology determines a minimum bandwidth demand based on the average bandwidth consumption and sets a dynamic voltage and frequency scaling point based on the minimum bandwidth demand.

公开(公告)号：WO2022271445A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/032544

申请日：2022-06-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： TSIEN, Benjamin ,  APTE, Amit P.

IPC: G06F1/3296 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0833 ,  G06F13/26

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

公开(公告)号：WO2022212089A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/020930

申请日：2022-03-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BRANDL, Kevin M. ,  PAUL, Indrani ,  CHITTILAPPILLY, Jean J. ,  VERMA, Abhishek Kumar ,  MAGRO, James R. ,  PILAR, Kavyashree

IPC: G06F1/3234 ,  G06F1/3293 ,  G06F1/3296 ,  G06F1/3225 ,  G06F1/3243 ,  G06F1/3275 ,  G06F13/1668 ,  G06F3/0625 ,  G11C11/40615

Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.

公开(公告)号：WO2022108582A1

公开(公告)日：2022-05-27

申请号：PCT/US2020/061057

申请日：2020-11-18

Applicant: GOOGLE LLC

Inventor： BASEHORE, Derek ,  RAO, Sonny

IPC: G06F1/324 ,  G06F1/3225 ,  G06F1/3234 ,  G06F11/34 ,  G06F12/0897 ,  G06F3/06

Abstract: Techniques and apparatuses are described that use transaction queue lengths to alter a clock frequency that controls access to a memory (112, 114) of an electronic device (102). Techniques include detecting (502) that a transaction queue threshold has been violated, initiating (504) a counter to measure a time duration, determining (506) that the transaction queue threshold continues to be violated for the time duration and, in response, altering (508) the clock frequency (210, 212) that controls access to the memory (112, 114) of the electronic device (102).