APPARATUS FOR AND METHOD OF SYNCHRONIZING A CLOCK SIGNAL
    1.
    发明申请
    APPARATUS FOR AND METHOD OF SYNCHRONIZING A CLOCK SIGNAL 审中-公开
    同步时钟信号的方法和方法

    公开(公告)号:WO1993019548A1

    公开(公告)日:1993-09-30

    申请号:PCT/US1993000413

    申请日:1993-01-21

    Applicant: MOTOROLA, INC.

    CPC classification number: H04L7/0337

    Abstract: The present disclosure includes a discussion of a method of synchronizing a sampling clock signal to a received data signal (131). The clock recovery circuit (127) generates several clock signals (339, 341, 343, 345) at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry (127) generates error signals (347, 349, 351, 353) representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals (347, 349, 351, 353) are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit (127) then adjusts or maintains the phase of the symbol clock (139) to provide the optimal sampling phase.

    APPARATUS AND METHOD FOR RECOVERING A TIME-VARYING SIGNAL USING MULTIPLE SAMPLING POINTS
    2.
    发明申请
    APPARATUS AND METHOD FOR RECOVERING A TIME-VARYING SIGNAL USING MULTIPLE SAMPLING POINTS 审中-公开
    使用多个采样点恢复时变信号的装置和方法

    公开(公告)号:WO1993007690A1

    公开(公告)日:1993-04-15

    申请号:PCT/US1992006995

    申请日:1992-08-19

    Applicant: MOTOROLA, INC.

    CPC classification number: H04L27/22 H04L7/042 H04L7/10 H04L27/2275

    Abstract: The present invention presents an apparatus and method for recovering symbols in a data packet (101) transmitted to a receiver from a remote signal source (204) in a time-varying channel using multiple sampling points. In a digital cellular radiotelephone TDMA system, the receiver (202) performs a complex correlation on the desired slot sync word (DSSW) and the coded digital verification color code (CDVCC) in the data packet (101), and on the adjacent slot sync word (ASSW) in an adjacent data packet (102) to produce a first, second and third optimum sampling point, respectively. The data packet (101) is divided into four regions (A, B, C and D). The symbols in each region (A, B, C and D) are serially recovered using one or more of the multiple sampling points depending on the quality of the sampling point adjacent to each region (A, B, C and D).

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