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公开(公告)号：WO2018201409A1
公开(公告)日：2018-11-08
申请号：PCT/CN2017/083101
申请日：2017-05-04
Inventor： CHEN, Jie , CHEN, Yu , DU, Dongyang , JAYASINGHE, Keeth Saliya , TAN, Jun
IPC: H04L1/00
Abstract: It is provided a method, comprising generating a first set of one or more check bits based on one or more information bits of a first segment of an information block of K information bits; constructing a code block comprising the K information bits of the information block and the first set of check bits; performing polar encoding of the code block, wherein the first set of check bits are generated without taking into account any of the one or more information bits of a second segment of the information block;； each of the information bits of the first segment is different from each of the information bits of the second segment;； each of the information bits of the first segment is distributed in the code block on less reliable bit positions for the polar encoding than each of the information bits of the second segment.
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公开(公告)号：WO2019000190A1
公开(公告)日：2019-01-03
申请号：PCT/CN2017/090091
申请日：2017-06-26
Inventor： JAYASINGHE, Keeth Saliya , CHEN, Yu , CHEN, Jie , DU, Dongyang
IPC: H03M13/09
Abstract: A method for encoding a sequence of control information bits, the method comprising: generating a first sequence of bits comprising a sequence of predetermined bits for an encoder and a sequence of control information bits; generating a sequence of error detection and/or error correction bits based on the sequence of predetermined bits for the encoder and the sequence of control information bits; and encoding a redistributed sequence comprising the sequence of predetermined bits for the encoder, the sequence of control information bits and the sequence of error detection and/or error correction bits.
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3.发明申请
公开(公告)号：WO2018218621A1
公开(公告)日：2018-12-06
申请号：PCT/CN2017/086884
申请日：2017-06-01
Inventor： DU, Dongyang , JAYASINGHE, Keeth Saliya , SUN, Jingyuan , CHEN, Jie , CHEN, Yu
IPC: H04W72/04
Abstract: An apparatus and method that performs the steps of calculating, by an entity, one or more assistance bits, and allocating, by the entity, the one or more assistance bits. The one or more assistance bits comprise one or more primary parts and one or more secondary parts, wherein the one or more primary parts and the one or more secondary parts are used for error correction and/or error detection.
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Patent Agency Ranking
公开(公告)号：WO2018201408A1
公开(公告)日：2018-11-08
申请号：PCT/CN2017/083099
申请日：2017-05-04
Inventor： JAYASINGHE, Keeth Saliya , CHEN, Yu , DU, Dongyang , CHEN, Jie
IPC: H03M13/09
Abstract: A method comprising: determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.
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公开(公告)号：WO2018201377A1
公开(公告)日：2018-11-08
申请号：PCT/CN2017/083003
申请日：2017-05-04
Inventor： JAYASINGHE, Keeth Saliya , CHEN, Yu , DU, Dongyang , CHEN, Jie
CPC classification number: H03M13/13 , H03M13/09 , H03M13/2906 , H04L1/00 , H04L1/0041 , H04L1/0057 , H04L1/0061
Abstract: It is provided a method, comprising generating J addon bits if K information bits are sequentially inputted into a generating means comprising J registers; retrieving J * addon bits from the J registers after at least one of the K information bits had been inputted into the generating means and before the K information bits are inputted into the generating means; constructing a codeblock comprising each of the K information bits, the J addon bits, and the J * addon bits, wherein each of the K information bits, the J addon bits, and the J * addon bits is at a respective predetermined position of the codeblock; polar encoding the codeblock.
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公开(公告)号：WO2018126428A1
公开(公告)日：2018-07-12
申请号：PCT/CN2017/070377
申请日：2017-01-06
Inventor： SUN, Jingyuan , ZHANG, Yi , ZENG, Xiangnian , JIANG, Wei , DU, Dongyang , JAYASINGHE, Keeth Saliya
IPC: H03M13/11
Abstract: A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.
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公开(公告)号：WO2018126458A1
公开(公告)日：2018-07-12
申请号：PCT/CN2017/070487
申请日：2017-01-06
Inventor： DU, Dongyang , SUN, Jingyuan , ZHANG, Yi , JIANG, Wei , ZENG, Xiangnian
IPC: H04L1/18
CPC classification number: H04L1/0057 , H04L1/0071 , H04L1/1819 , H04L1/1845
Abstract: Various communication systems may benefit from improved performance. For example, communication systems may benefit an improved transmission in which the data bits are reordered to increase the reliability of the transmitted data bits. A method, in certain embodiments, may include transmitting during a first transmission a plurality of bits encoded as a polar code from a user equipment or a network entity to the network entity or the user equipment. The method may also include transmit during a second transmission at least part of the plurality of bits encoded as the polar code or another polar code. The at least part of the plurality of bits are sorted in a different order before the encoding of the second transmission than an order in which the plurality of bits were positioned during the first transmission.
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公开(公告)号：WO2018165894A1
公开(公告)日：2018-09-20
申请号：PCT/CN2017/076750
申请日：2017-03-15
Inventor： JAYASINGHE, Keeth Saliya , CHEN, Jie , DU, Dongyang , CHEN, Yu
IPC: H03M13/29
Abstract: A method for encoding a sequence of control information bits comprising: generating a sequence of error detection bits based on the sequence of control information bits; generating a sequence of error correction bits based on the sequence of control information bits; and distributing the sequence of error detection bits and the sequence of error correction bits between the sequence of control information bits to form a combined sequence of bits, such that the bit order of the combined sequence of bits following the distribution enables an error detection check to be performed before or after a first error correction check bit.
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