公开(公告)号：WO2014168838A3

公开(公告)日：2014-12-11

申请号：PCT/US2014033051

申请日：2014-04-04

Applicant: QUALCOMM INC

Inventor： RASOULI SEID HADI ,  DATTA ANIMESH ,  SHAH JAY MADHUKAR ,  SAINT-LAURENT MARTIN ,  PARKAR PEEYUSH KUMAR ,  BAPAT SACHIN ,  VILANGUDIPITCHAI RAMAPRASATH ,  ABU-RAHMA MOHAMED HASSAN ,  PATEL PRAYAG BHANUBHAI

IPC: H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit (100) including a logic gate (133) responsive to a clock signal (103) and to a control signal (104). The circuit also includes a master stage (101) of a flip-flop. The circuit further includes a slave stage (102) of the flip-flop responsive to the master stage. The circuit further includes an inverter (109) responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage (101) and to the slave stage (102) of the flip-flop. The master stage is responsive to the control signal to control (122out) the slave stage.

Abstract translation: 一种包括响应时钟信号（103）和控制信号（104）的逻辑门（133）的电路（100）。 电路还包括触发器的主级（101）。 电路还包括响应于主级的触发器的从级（102）。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器（109）。 逻辑门的输出和时钟信号的延迟版本被提供给主级（101）和触发器的从级（102）。 主级响应控制信号来控制（122输出）从动级。

公开(公告)号：WO2014194007A2

公开(公告)日：2014-12-04

申请号：PCT/US2014039867

申请日：2014-05-28

Applicant: QUALCOMM INC

Inventor： BELLUR KASHYAP RAMACHANDRA ,  CHINTARLAPALLI REDDY HARIKRISHNA ,  SAINT-LAURENT MARTIN ,  KAMAL PRATYUSH ,  PATEL PRAYAG BHANUBHAI ,  TERZIOGLU ESIN

IPC: G06F17/50

CPC classification number: H03K3/037 ,  G06F17/5068 ,  G06F17/5081 ,  H03K3/012 ,  H03K3/356

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract translation: 电路包括脉冲锁存电路。 脉冲锁存电路包括第一多个晶体管。 第一多个晶体管中的一个或多个是扩散长度（LOD）保护的。