公开(公告)号：WO2007149808A3

公开(公告)日：2008-02-07

申请号：PCT/US2007071450

申请日：2007-06-18

Applicant: QUALCOMM INC ,  SAINT-LAURENT MARTIN ,  BASSETT PAUL ,  PATEL PRAYAG

Inventor： SAINT-LAURENT MARTIN ,  BASSETT PAUL ,  PATEL PRAYAG

IPC: G01R31/3185

CPC classification number: G01R31/318552 ,  G01R31/3025 ,  G01R31/318575

Abstract: A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

Abstract translation: 逻辑器件包括数据输入，扫描测试输入，时钟解复用器和主锁存器。 时钟解复用器响应时钟输入以选择性地提供第一时钟输出和第二时钟输出。 主锁存器耦合到数据输入和扫描测试输入，并包括一个输出。 主锁存器响应于时钟解复用器的第一时钟输出和时钟多路分解器的第二时钟输出，以选择性地将数据输入或扫描测试输入耦合到输出。

公开(公告)号：WO2009135226A3

公开(公告)日：2010-09-10

申请号：PCT/US2009043913

申请日：2009-05-14

Applicant: QUALCOMM INC ,  SAINT-LAURENT MARTIN ,  MOHD BASSAM JAMIL ,  BASSETT PAUL

Inventor： SAINT-LAURENT MARTIN ,  MOHD BASSAM JAMIL ,  BASSETT PAUL

IPC: G06F1/04 ,  G06F1/32 ,  G06F17/50 ,  H03K19/017

CPC classification number: H03K19/0016 ,  G06F1/04

Abstract: A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

Abstract translation: 公开了时钟选通系统和方法。 在特定实施例中，系统包括输入逻辑电路，该输入逻辑电路具有至少一个输入端以接收至少一个输入信号并在内部使能节点具有输出。 保持器电路包括响应于门控时钟信号的至少一个开关元件，并且耦合到内部使能节点以选择性地保持内部使能节点处的逻辑电压电平。 该系统还包括响应于输入时钟信号和内部使能节点处的逻辑电压电平的选通元件，以产生门控时钟信号。

公开(公告)号：WO2014150448A2

公开(公告)日：2014-09-25

申请号：PCT/US2014023290

申请日：2014-03-11

Applicant: QUALCOMM INC

Inventor： WANG YUHE ,  PEDRALI-NOY MARZIO ,  HUANG XUHAO ,  SAINT-LAURENT MARTIN ,  CHEN XUFENG

IPC: G05F1/565

CPC classification number: G05F1/462 ,  G05F1/565 ,  G05F1/575

Abstract: Techniques are described that embed a digital assisted regulator with an LDO regulator on a chip without requiring a capacitor external to the chip and to regulate a voltage without undershoot. The digital assisted regulator responds to information regarding operation of the LDO regulator and to a signal that provides advance notification of a load change. When the advance notification signal is received, the digital assisted regulator pulls a circuit's supply voltage up to a chip's incoming supply voltage. When the correct operating voltage has been reached and any undershoot problem removed, the digital assisted regulator balances the current it provides with the current provided by the LDO regulator, to allow a quick response time for other load changes. Also, bandwidth of an LDO regulator may be expanded by use of an advance notice signal to increase bias current of an LDO output device to meet an upcoming load change.

Abstract translation: 描述了将芯片上的LDO调节器嵌入数字辅助调节器的技术，而不需要芯片外部的电容器并且调节电压而不会下冲。 数字辅助稳压器响应关于LDO调节器的操作的信息以及提供负载变化提前通知的信号。 当接收到提前通知信号时，数字辅助调节器将电路的电源电压提升到芯片的输入电源电压。 当达到正确的工作电压并消除任何下冲问题时，数字辅助调节器将其提供的电流与LDO调节器提供的电流平衡，以允许其他负载变化的快速响应时间。 此外，LDO调节器的带宽可以通过使用提前通知信号来扩展，以增加LDO输出设备的偏置电流以满足即将到来的负载变化。

公开(公告)号：WO2013070783A3

公开(公告)日：2013-11-28

申请号：PCT/US2012063967

申请日：2012-11-07

Applicant: QUALCOMM INC

Inventor： SAINT-LAURENT MARTIN

IPC: H03L7/00

CPC classification number: H03L7/00 ,  G06F1/10 ,  H03L7/0995 ,  H03L7/16 ,  H03L2207/06

Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.

Abstract translation: 一种方法包括确定控制设置并且在一段时间之后选择性地停止振荡器的振荡。 振荡器被配置为在该时间段之后保持在活动模式。 该方法还包括将控制设置应用于振荡器。

公开(公告)号：WO2009058995A2

公开(公告)日：2009-05-07

申请号：PCT/US2008081778

申请日：2008-10-30

Applicant: QUALCOMM INC ,  SAINT-LAURENT MARTIN ,  BASSETT PAUL D

Inventor： SAINT-LAURENT MARTIN ,  BASSETT PAUL D

IPC: H03K5/135 ,  H03K3/037

CPC classification number: H03K3/037 ,  H03K3/356043 ,  H03K5/135

Abstract: The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse generator includes a second latch that has characteristics matching the first latch.

Abstract translation: 本公开包括使用锁存器的锁存结构和自调整脉冲发生器。 在一个实施例中，系统包括第一锁存器和连接到第一锁存器的定时信号的脉冲发生器。 脉冲发生器包括具有与第一锁存器匹配的特性的第二锁存器。

公开(公告)号：WO2007147017A3

公开(公告)日：2008-02-28

申请号：PCT/US2007071147

申请日：2007-06-13

Applicant: QUALCOMM INC ,  SAINT-LAURENT MARTIN ,  ZHANG YAN

Inventor： SAINT-LAURENT MARTIN ,  ZHANG YAN

IPC: H04L7/02 ,  G06F1/08 ,  H03K5/1252 ,  H04L7/00

CPC classification number: H04L7/0083 ,  G06F1/08

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output in response to a low phase input level in the first clock output. For a limited period of time, a low phase output level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在从第一时钟输入切换到驱动时钟多路复用器的第二时钟输入时发生减小的毛刺。 时钟多路复用器接收第一时钟输入并提供时钟输出，并响应于第一时钟输出中的低相位输入电平确定时钟输出中的低相位输出电平。 在有限的时间段内，不管第一时钟输入信号的相位电平如何，都会强制执行低相输出电平。 时钟复用器接收第二时钟输入并确定第二时钟输入信号中的低相位输入电平。 响应于第二时钟输入而提供时钟输出的切换发生在第二时钟输入信号中的低相位输入电平期间。 然后，时钟复用器的输出跟随第二时钟信号的相位电平。

公开(公告)号：WO2014168838A3

公开(公告)日：2014-12-11

申请号：PCT/US2014033051

申请日：2014-04-04

Applicant: QUALCOMM INC

Inventor： RASOULI SEID HADI ,  DATTA ANIMESH ,  SHAH JAY MADHUKAR ,  SAINT-LAURENT MARTIN ,  PARKAR PEEYUSH KUMAR ,  BAPAT SACHIN ,  VILANGUDIPITCHAI RAMAPRASATH ,  ABU-RAHMA MOHAMED HASSAN ,  PATEL PRAYAG BHANUBHAI

IPC: H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit (100) including a logic gate (133) responsive to a clock signal (103) and to a control signal (104). The circuit also includes a master stage (101) of a flip-flop. The circuit further includes a slave stage (102) of the flip-flop responsive to the master stage. The circuit further includes an inverter (109) responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage (101) and to the slave stage (102) of the flip-flop. The master stage is responsive to the control signal to control (122out) the slave stage.

Abstract translation: 一种包括响应时钟信号（103）和控制信号（104）的逻辑门（133）的电路（100）。 电路还包括触发器的主级（101）。 电路还包括响应于主级的触发器的从级（102）。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器（109）。 逻辑门的输出和时钟信号的延迟版本被提供给主级（101）和触发器的从级（102）。 主级响应控制信号来控制（122输出）从动级。

公开(公告)号：WO2014194007A2

公开(公告)日：2014-12-04

申请号：PCT/US2014039867

申请日：2014-05-28

Applicant: QUALCOMM INC

Inventor： BELLUR KASHYAP RAMACHANDRA ,  CHINTARLAPALLI REDDY HARIKRISHNA ,  SAINT-LAURENT MARTIN ,  KAMAL PRATYUSH ,  PATEL PRAYAG BHANUBHAI ,  TERZIOGLU ESIN

IPC: G06F17/50

CPC classification number: H03K3/037 ,  G06F17/5068 ,  G06F17/5081 ,  H03K3/012 ,  H03K3/356

Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.

Abstract translation: 电路包括脉冲锁存电路。 脉冲锁存电路包括第一多个晶体管。 第一多个晶体管中的一个或多个是扩散长度（LOD）保护的。