公开(公告)号：WO2009015326A2

公开(公告)日：2009-01-29

申请号：PCT/US2008/071155

申请日：2008-07-25

Applicant: QUALCOMM Incorporated ,  HOFMANN, Richard, Gerard ,  BRIDGES, Jeffrey, Todd

Inventor： HOFMANN, Richard, Gerard ,  BRIDGES, Jeffrey, Todd

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.

Abstract translation: 不同的软件应用可以使用具有小于处理器复合体的最坏情况关键定时路径的关键定时路径的指令集。 对于这样的应用，可以降低电源电压，同时仍然保持满足应用的性能要求所需的时钟频率。 为了降低电源电压，使用自适应电压缩放方法。 从多个关键路径中选择关键路径用于分析仿真逻辑以在片上功能操作期间确定所选择的关键路径的属性。 所选择的关键路径代表在程序执行期间正在运行的最坏情况的关键路径。 在片上功能操作期间，响应于属性来控制电压，其中电压向与多个关键路径相关联的电力域提供电力。 基于指令集的使用，电压的降低可以减少功耗，从而延长电池寿命。

公开(公告)号：WO2006102635A2

公开(公告)日：2006-09-28

申请号：PCT/US2006/010952

申请日：2006-03-23

Applicant: QUALCOMM INCORPORATED ,  SMITH, Rodney, Wayne ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  SARTORIUS, Thomas, Andrew

Inventor： SMITH, Rodney, Wayne ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  SARTORIUS, Thomas, Andrew

CPC classification number: G06F9/3806 ,  G06F9/3848

Abstract: A Branch Target Address Cache (BTAC) stores at least two branch target addresses in each cache line. The BTAC is indexed by a truncated branch instruction address. An offset obtained from a branch prediction offset table determines which of the branch target addresses is taken as the predicted branch target address. The offset table may be indexed in several ways, including by a branch history, by a hash of a branch history and part of the branch instruction address, by a gshare value, randomly, in a round-robin order, or other methods.

Abstract translation: 分支目标地址缓存（BTAC）在每个高速缓存行中存储至少两个分支目标地址。 BTAC由截断的分支指令地址索引。 从分支预测偏移表获得的偏移决定了哪个分支目标地址被作为预测分支目标地址。 偏移表可以通过分支历史，分支历史和部分分支指令地址的散列，以循环次序或其他方法随机的gshare值被索引。

公开(公告)号：WO2006084288A2

公开(公告)日：2006-08-10

申请号：PCT/US2006/006993

申请日：2006-02-03

Applicant: QUALCOMM Incorporated ,  SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Robert ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

Inventor： SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Robert ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3804

Abstract: A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

Abstract translation: 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。

公开(公告)号：WO2007051204A1

公开(公告)日：2007-05-03

申请号：PCT/US2006/060370

申请日：2006-10-30

Applicant: QUALCOMM INCORPORATED ,  PHAN, Michael, ThaiThanh ,  CHAI, Chiaming ,  BRIDGES, Jeffrey, Todd ,  FISCHER, Jeffrey, Herbert

Inventor： PHAN, Michael, ThaiThanh ,  CHAI, Chiaming ,  BRIDGES, Jeffrey, Todd ,  FISCHER, Jeffrey, Herbert

IPC: G11C15/04

CPC classification number: G11C15/00 ,  G11C8/12 ,  G11C15/04

Abstract: A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.

Abstract translation: CAM组在功能上划分为两个或更多个子行，不复制CAM驱动电路，禁止该组中的所有匹配线放电电路，并且选择性地使得放电电路在包含子行的条目中使能。 至少一个选择性致动的切换电路插入在子组的放电电路中的每个放电比较器的虚拟接地节点和电路接地之间。 当开关电路处于非导通状态时，虚拟接地节点保持在足够高于电路接地的电压电平，以防止在CAM访问时间内放电连接的匹配线。 当开关电路处于导通状态时，虚拟接地节点被拉到电路接地，并且连接的匹配线可能被误比较地放电。 可以从地址位解码的控制信号被分配给切换电路以定义CAM子库。

公开(公告)号：WO2006130466A2

公开(公告)日：2006-12-07

申请号：PCT/US2006/020440

申请日：2006-05-24

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne

Inventor： SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne

CPC classification number: G06F9/3844

Abstract: A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.

Abstract translation: 微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令， 在分支目标缓存中丢失。 因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。 因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

公开(公告)号：WO2006113420A2

公开(公告)日：2006-10-26

申请号：PCT/US2006/014042

申请日：2006-04-14

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  DOCKSER, Kenneth, Alan ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

Inventor： SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  DOCKSER, Kenneth, Alan ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

IPC: G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

Abstract: A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

Abstract translation: 被构造为接收一个或多个操作数作为输入的条件指令，如果满足条件则向目标输出对操作数执行的操作的结果，并且如果条件满足则不提供输出 不满意，被执行以便无条件地向目标提供输出。 条件指令获取目标的先前值（即，由更新该目标的条件指令之前的最近指令产生的值）。 条件被评估。 如果条件满足，则执行操作并将操作的结果输出到目标。 如果条件不满足，则将先前值输出到目标。 在条件评估之前，后续指令可能依赖目标作为操作数源（无论写入寄存器还是转发给指令）。

公开(公告)号：WO2007085010A3

公开(公告)日：2007-07-26

申请号：PCT/US2007/060814

申请日：2007-01-22

Applicant: QUALCOMM INCORPORATED ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  SARTORIUS, Thomas, Andrew

Inventor： DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  SARTORIUS, Thomas, Andrew

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.

公开(公告)号：WO2007016393A2

公开(公告)日：2007-02-08

申请号：PCT/US2006/029523

申请日：2006-07-26

Applicant: QUALCOMM INCORPORATED ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne ,  SARTORIUS, Thomas, Andrew

Inventor： BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne ,  SARTORIUS, Thomas, Andrew

IPC: G06F9/38

CPC classification number: G06F9/30149 ,  G06F9/3816 ,  G06F9/382

Abstract: A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.

Abstract translation: 固定数量的可变长度指令存储在指令高速缓存的每一行中。 可变长度指令沿预定边界排列。 由于行中的每条指令的长度以及指令占用的存储器的跨度是未知的，因此下一个跟随指令的地址被计算并与高速缓存行一起存储。 在将指令置于高速缓存之前，确定指令边界，对准指令并计算下一个提取地址在预解码器中执行。

公开(公告)号：WO2006096569A2

公开(公告)日：2006-09-14

申请号：PCT/US2006/007759

申请日：2006-03-03

Applicant: QUALCOMM Incorporated ,  SMITH, Rodney, Wayne ,  STEMPEL, Brian, Michael ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  SARTORIUS, Thomas, Andrew

Inventor： SMITH, Rodney, Wayne ,  STEMPEL, Brian, Michael ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  SARTORIUS, Thomas, Andrew

CPC classification number: G06F12/1063 ,  G06F9/321 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/6028

Abstract: A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.

Abstract translation: 流水线处理器包括指令高速缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC获取的阶段。 为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC的获取导致从iCache获取分支指令与从BTAC获取所需的周期相关的量。 所公开的示例可以减少BTAC的写入地址或增加BTAC的获取地址，其量基本上对应于比BTAC提取所需的周期少一个量。

公开(公告)号：WO2006084289A3

公开(公告)日：2006-08-10

申请号：PCT/US2006/006994

申请日：2006-02-03

Applicant: QUALCOMM INCORPORATED ,  BRIDGES, Jeffrey, Todd ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew

Inventor： BRIDGES, Jeffrey, Todd ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew

IPC: G06F9/312

Abstract: One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose register file utilizes register renaming or a reorder buffer, data from plural misaligned memory access operations are assembled directly in a fractional-word writable architected register, without the need to fully exception check both misaligned memory access operations before performing the first memory access operation.